The IRPS Reliability Year-in-Review (YiR) session consists of 3 presentations reviewing the past year's reliability work by experts in the field for areas of high interest. It is an excellent augmentation to the tutorial sessions immediately preceding, and attendees may obtain keen reliability insights in a short amount of time.

(YIR1) 27th March 3:00 PM - 3:50 PM
Soft Error in Planar, FDSOI, FinFET, and GAA

Taiki Uemura (Samsung Electronics)

Abstract: Radiation effect in semiconductor devices is a critical concern in high-performance computing (HPC) and automotive applications. The HPC scale grows more than Moor’s law, an HPC system has over 8 million semiconductor devices, and the required quality is extremely high in a semiconductor device. Screening and process modification are not able to prevent soft errors; soft error is the principal concern in HPC reliability. This YIR will cover state-of-the-art of soft error technology in the advanced technology as applied to HPC. Automotive is another application that has a huge concern about soft error. Qualification of automotive devices is compliance with ISO26262 and AEC-Q100. The two standards follow a JEDEC standard, JESD89 (Measurement and Reporting of Alpha Particle and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices). JESD89 has been updated 2021 (JESD89B), and this YIR explains the update in JESD89. This YIR will cover the new potential radiation effect: X-ray effect and SEFI in DRAM, and SEE in MRAM.

(YIR2) 27th March 3:50 PM - 4:40 PM
SiC Devices

Daniel J. Lichtenwalner (Wolfspeed, A Cree Company)

Abstract: Recent years have seen much focus on the advancement of SiC power devices from niche applications to mainstream power conversion applications. SiC diodes and MOSFETs are key components in power conversion devices and modules for various industrial applications ranging from solar, wind, computer servers, traction, among others. These devices have shown their ability to provide energy efficiency savings due to their low on-state resistance in high voltage applications (typical product offerings range from 650V to 3.3kV), and low switching energy losses. The performance benefits of SiC power devices in efficiency compared to competing silicon-based devices is clear. The recent push for SiC power MOSFETs in automotive applications (chargers, motor drives) has increased the focus on ensuring low (ppm) failure rates, and consequently demands a more complete understanding of all failure mechanisms. Thus the last few years have seen a multitude of studies aimed to fully characterize the complete device operating conditions in static and dynamic device operation. Both intrinsic and extrinsic failure modes have been studied in much more detail due to these demands of automotive products and their qualification criteria. In this review, a summary of the many important reliability tests for SiC MOSFETs will be discussed, explaining differences between silicon and SiC-based devices, and then focusing on threshold stability tests that are critical for SiC MOS devices. Namely, the issue of threshold drift under gate switching (gate switching instability, GSI) has been recently observed to be unlike that experienced in silicon devices, and various studies have been published which elucidate the effects of this failure mode, with some explanation regarding the origins of this failure mechanism. The results presented in these recent studies will be summarized.

(YIR3) 27th March 4:40 PM - 5:30 PM
FEOL reliability of fin, NW, NS FETs

Stanislav Tyaginov, Michiel Vandemaele, Erik Bury (imec)

Abstract: The arrival of the mobile era and the internet of things requires long battery life for electronic components and low OFF currents. Thus, transistors are optimized by introducing novel device topologies such as fin, nanowire (NW), nanosheet (NS), and forksheet (FS) field-effect-transistors (FETs). They are designed to improve electrostatic channel control and result in a steeper sub-threshold slope and hence an improved ratio between ON and OFF currents. Thereby a reduction of the device power consumption and further scaling of the supply and threshold voltages becomes possible. In addition to such tangible product parameters as performance and power consumption, reliability specifications are the essential metric required for the introduction of each new VLSI node. In this year-in-review we provide a summary of recent papers devoted to front-end-of-line (FEOL) reliability concerns in fin, NW, NS, and FS FETs: bias temperature instability (BTI), hot-carrier degradation (HCD), OFF-state stress (OSS), and self-heating (SH), as well as their intricate superpositions. This presentation rests on three pillars: (i) experimental investigations of the degradation issues in the novel devices, (ii) strategies on how to alleviate these degradation effects and optimize the device architecture, and (iii) predictive lifetime modeling for FETs subjected to BTI, HCD, OSS, and SH.

Archives

IRPS 2022 Year in Review

• 3D IC Packaging by Kangwook (Kriss) Lee, (SK Hynix)

• Emerging Memory Reliability (MRAM, RRAM, PCM, Ferroelectrics) by Shimeng Yu, (Georgia Tech)

• Reliability and aging aware designs / Circuit reliability by Evelyn Landman, (Protean Tecs)

IRPS 2021 Year in Review

• FinFET vs GAA : Main reliability Differences and Concerns by Adrian Chasin (imec)

• Reliability Testing: Considerations for Physics-Based Reliability Testing Development by Derek W. Slottke (Intel)

• Industry Council on ESD Target Levels: Review of Achievements, Activities, and Initiatives by Charvaka Duvvury (ESD consulting)