Highlighted Papers
Inside Program: Conference Program l Keynote Speakers l Tutorials
Workshops l Year in Review l Highlighted Paper l Invited Speakers
(4A.1 - GD) 3:40pm, April 1st
(Invited) Interplay between charge defects and ferroelectric reliability: From wake-up, imprint, fatigue, to breakdown
Comprehensive defect-dominant ferroelectric reliability model
Reveal the interplay of fast and slow traps and their roles in the wake-up and fatigue phenomena
(4C.3 - RE) 4:30pm, April 1st
(Invited) Safety in Memory Architectures for Automotive Applications
Faults in High Computer Memory Subsystems
Failure rates?
Safety Mechanism?
Diagnostic Coverage?
How does it Translate to Component Spec?
Tradeoff between Performance and Safety
System Resiliency
(4B.4 - FA) 4:35pm, April 1st
Recent developments in EOTPR towards a fully automated tool for high volume failure analysis
This paper is about the advancement of EOTPR (electro optical terahertz pulsed reflectometry), the fault isolation tool for FA
Throughput and accuracy improved for EOTPR by introducing QuickSim and QuickView software packages
A case study was presented by comparing a failed CoWoS unit with a reference that pinpointed failure
(6A.1 - TX) 10:50am, April 2nd
Impact of Mechanical Stress on IGZO TFTs: Enhancing PBTI Degradation
Analysis of mechanical stress effects on IGZO FETs
Comprehensive experimental work supporting theoretical insights
Mechanical stress induces Vt shift via bandgap widening without impacting SS or ION
Degradation primarily affects the channel rather than the contacts
Combined mechanical and electrical stress exacerbates PBTI degradation
(6B.1 - EM) 10:50am, April 2nd
Enhanced Memory Performance in Ferroelectric NAND applications: The Role of Tunnel Dielectric position for Robust 10-year Retention
Placing the dielectric insert for MW enhancement in the middle of the FE gate stack reduces depolarization significantly by preventing the de-trapping of the MW enhancing charges. Thereby, energetically stabilizing the MW enhancement.
(6C.3 - MB) 11:40am, April 2nd
Local Electric Field–Aware 3D TDDB model for BEOL reliability predictions
Local Electric Field–Aware 3D TDDB Model (LEFAM) accounts for non-uniform electric fields near lines and vias, and simulates local defect generation dynamics, incorporating the impact of geometrical variations like line-edge roughness (LER) and via misalignment (VM)
It Incorporates local defect density and electric field variations for a more realistic approach, and combines the finite element method (FEM) to model local electric fields with the Monte Carlo method for defect generation
It uses a percolation model for Time-Dependent Dielectric Breakdown (TDDB) simulations and predicts the impact of geometric variations on BEOL reliability, aiding scaling to future technology nodes
(7A.2 - PK) 2:00pm, April 2nd
CoWoS Package Reliability Risk Assessment & Mitigation from Mechanical Perspectives
CoWoS (chip-on-wafer-on-substrate) enables integration of multiple chips in a package and powers the current generative AI applications
CoWos reliability challenges arise due to complex packages and large package sizes
In this work, thermomechanical property measurements are correlated with level of stress during reliability tests for risk prediction
(7B.2 - CR) 2:00pm, April 2nd
Investigation of Cryogenic Aging in 28nm CMOS: Suppression of BTI and HCD in Circuits and SRAM
A novel array of ring-oscillators designed in 28 nm commercial tech
RO aged at several voltages and cryogenic temperatures using Lakeshore CPX-LVT cryostat
Equivalent aging at cryogenic temperatures used in 6T SRAM for performance evaluation
(7C.3 - ESD) 2:25pm, April 2nd
Novel Trigger Circuit & SCR Device Co-Engineering Based Local (I/O-VSS & I/O-VDD) ESD Clamp Concepts with improved Latch-up Susceptibility, Lower Leakage and Lower Capacitance for Ultra High Speed I/Os
Low leakage (-50%), low capacitance (-35%)
Latch-up immunity improvement
High holding voltage
(8C.1 - SER) 3:15pm, April 2nd
Improved Silent Data Error Detection through Test Optimization using Reinforcement Learning
Silent Data Errors (SDE) are a serious concern for at-scale computing in data centres because they may cause data loss or data corruption
It is therefore critical to identify defective devices that may experience SDE events and remove them before customer workloads are impacted
This paper reports the results of applying reinforcement learning methods (RL) to a family of open-source Eigen tests, and how this work improved the effectiveness of these tests at detecting SDE events
(8A.2 - GaN) 3:40pm, April 2nd
RTN Analysis of Schottky p-GaN gate HEMTs Under Forward Gate Stress: Impact of Temperature
Novel insight into defect generation in GaN p-gate gates
(8B.4 - PI) 4:30am, April 2nd
Hot Carrier Degradation and performance boost on Si Channel nFET Gate-All-Around Nanosheet Devices
Joint performance / HC degradation optimization is proposed by proper junction and inner spacer optimization
Novel and attractive for the GAA NS community and beyond
(9C.2 - NC) 9:35am, April 3rd
Effects of Temperature and Device-to-Device in pFET-Based Bias Temperature Instability Reservoir Computing
Explores reliability of novel computing circuits while accounting for device nonidealities
(10A.2 - RT) 11:15pm, April 3rd
Enhancing Reliability Testing of Power IC and Power Devices for AI Hardware: Addressing Gate Oxide Defects, Transient Voltage Overshoot, and BVDSS Instability
This paper addresses three major reliability issues in power ICs, smart power devices and gives a very good insight in the testing methodology and explanation of the results including mitigation of the reliability issues
Transient voltage fault tolerance is an important topic to address for multiple market segments and has a general relevance
(10B.2 - PR) 11:15am, April 3rd
(Invited) Enhancing Automotive Product Quality Through Machine Learning-Based Methodology
This paper demonstrate the capability of machine learning on:
Yield Improvement: Identifies key process factors through multi-dimensional analysis
DPPM Reduction: Screens latent defects and identifies IC groups tolerating higher DVS levels
Early Aging Detection: Enhances sensitivity to detect aging failures, ensuring wear-out quality
(11C.1 - RF) 1:35pm, April 3rd
Perspectives on GaN MISHEMT Power Amplifier vs Positive Gate Bias Instability
(11B.3 - MR) 2:25pm, April 3rd
Advanced RTN Analysis on 3D NAND Trench Devices using Physics-Informed Machine Learning Framework
Device-level study on RTN in 3D NAND Flash useful for further device optimizations
The developed measurement and analysis framework has been validated and proven to be highly efficient
