Workshops

Workshop WS1: RF reliability methodologies for GaN and CMOS

Moderators: Alexis Divay, CEA Leti - Enrico Zanoni, University of Padova

Abstract: The goal of this workshop is to spark a meaningful dialogue between the CMOS and III-V communities regarding the challenges of assessing device reliability under RF operating conditions and the methodologies for evaluating their lifetime. Reliability assessment in RF devices is particularly complex due to the diversity of mission profiles. Devices may operate under varying quiescent bias points, impedance environments, VSWR conditions, and even dynamic modulation schemes throughout their lifetime.

Reliability evaluations in silicon RF technologies often rely on SPICE-based mission profiles under continuous wave conditions, but this approach is limited by imprecise lifetime predictions in advanced nodes and the challenges of industrializing on-wafer RF measurements, despite their ability to provide detailed degradation insights. In GaN technologies, RF stress testing—whether on-wafer or packaged—reveals unique failure mechanisms absent in DC conditions, but challenges arise in modeling these effects due to the complex, broad timescales of trapping phenomena.

Although CMOS and GaN technologies exhibit different degradation mechanisms, they share similar mission profiles. With the rise of 5G (FR1 to FR3), devices must reliably handle high peak-to-average power ratios (PAPR) while ensuring accurate degradation modeling, even under low compression conditions. This workshop aims to explore general methodologies for lifetime assessment under RF power amplifier (PA) operation and to evaluate the feasibility of developing universal approaches across diverse transistor technologies, including GaN, CMOS, SiGe, and InP, despite their differing degradation mechanisms.

Workshop WS2: Silicon Prognostics - how to predict & what to prepare for in-field end of life?

Moderators: Robert Jin, NXP - Jyotika Athavale, Synopsys

Abstract: Silicon Prognostics or Silicon Lifecycle Management refers to the capability to predict imminent faults in silicon and apply that knowledge for predictive maintenance, functional safety, reliability prediction, quality improvement, and power optimization. The underlining technologies include built-in sensors, holistic integration from edge to the cloud, and algorithms to interpret the measured results. In this context, the workshop will try to provide an open forum to discuss topics such as:

• What are the key circuit characteristics to look for.
• The type of sensors and their strategic placement.
• The cost and benefit equation of implementing such solution.
• How to train the prediction model and the tolerance of false positive and negatives.
• How to build an ecosystem to make the data flow seamlessly without “harm”.

Workshop WS3: Neuromorphic computing: path to energy-efficient AI

Moderators: Gennadi Bersuker, M2D solutions - An Chen, IBM

Abstract: An immense amount of data currently processed by AI systems using conventional computers based on von Neumann architecture results in unsustainable energy consumption. An effective solution to this conundrum is provided by neuromorphic computing, which merges logic and memory storage operations. The memory state is determined by the magnitude of current through the cell material; therefore, the key issue is to identify and manage structural material changes responsible for charge transport modulations. The discussion is focused on methodology for identifying test conditions relevant to specific applications and test data analysis in connection to processes modifying current in given material stack.

Workshop WS4: Reliability implications of Design Technology Co-optimization (DTCO)

Moderators: Mehul Shroff, NXP - Yun Dai, Cadence

Abstract: Design Technology Co-Optimization (DTCO) plays a critical role in addressing reliability challenges in advanced semiconductor nodes. As feature sizes shrink, it ensures device reliability becomes increasingly complex due to factors such as increased variability, aging effects, and thermal-induced failures. DTCO integrates process technology insights with design methodologies to mitigate these issues, enabling optimized transistor architectures, interconnects, and layout designs that enhance both performance and reliability. By identifying potential failure mechanisms early in the design process, DTCO facilitates robust design solutions that improve quality and reliability.

In the context of reliability, DTCO emphasizes the co-optimization of key factors such as voltage scaling, power distribution, and thermal management. Advanced techniques, such as aging-aware simulation and electromigration-resistant interconnect design, are integrated into the DTCO workflow to address wear-out mechanisms. Furthermore, DTCO ensures that design rules and layout practices help win yield battles, ultimately delivering high-quality and reliable products. As advanced nodes face stringent reliability and quality requirements for applications like AI, automotive, and IoT, DTCO provides a framework to meet these demands without sacrificing performance or scalability. As the industry moves toward even smaller geometries and heterogeneous integration, DTCO will play a pivotal role in shaping the future of semiconductor innovation by fostering collaboration between design and process technology teams.

Workshop WS5: How to construct bath tub curve for advanced heterogenous integration IC products

Moderators: Richard Rao, Marvell - Jae-Gyung Ahn, AMD

Abstract: Traditionally, the IC product level reliability measured in FIT(Failure In Time) rate is dominated by the Si chip and the contributions to the FIT rate from the package is very minimal. For the AI chips with the advanced heterogeneous integration, it introduces many new reliability failure modes that can cause a significantly high FIT rates to the overall IC product.

In this workshop, we will discuss to construct the IC product bathtub curve by considering both the Si chip, package and chip to package interaction failure modes.

Proposed topics include but not limited to the following topics:
1. Si chip level failure rates due to TDDB, EM and HCI/BTI
2. Advanced package failure rates due to various levels of interconnects such as uBumps/C4 Bumps/TSV/RDL, interface delamination and die cracking, etc.
3. Chip to package interaction induced failure rates

Workshop WS6: Plasma Charging Damage and ESD, Help Each Other?

Moderators: Steven Sze Hang Poon, TSMC - Andreas Martin, Infineon

Abstract: As process scaling, advanced packaging, and specialized technologies continue to evolve, requirements for electrostatic discharge (ESD) and process-induced damage (PID) are being driven into unchartered territory. Although these two subjects are often discussed separately, the design techniques are highly related, and recent changes have made it necessary to consider the interactions between the two.

On the ESD side, high-speed I/Os and die-to-die I/Os in advanced packaging are both known to benefit substantially from CDM goal reductions. Success depends on tight control of ESD during manufacturing and accurate characterization of protection and victim devices. Much emphasis will be placed on using and perfecting the most effective designs and devices, which will be made more challenging as future advanced processes may require use of unfamiliar structures.

On the PID side, cross-domain signals in processes with deep n-wells have recently been identified as an increasingly difficult issue and cause of product fails. Such cross-domain signals, in various forms, are likely to appear in advanced packaging and process technologies. ESD and PID naturally interact as both are related to charging. Cross-domain interfaces are challenges to both, with similar design mitigation techniques. As CDM goals continue to reduce, ESD protection area will also reduce, making it necessary to consider PID as part of the overall risk assessment.

Discussion topics of this workshop will include:

 ESD challenges:

 New device types due to process scaling
 CDM goal reduction for high-speed IO
 ESD design for die-to-die IOs
 TLP of ESD protection elements

 PID challenges:

 Deep N-well-related: well-to-well, single well
 Advanced packaging, 3D integration
 New challenges from advanced scaling

 ESD-PID interaction:

 Impact of lowering CDM goal on IO PID protection
 Cross-domain checking methodology

Workshop WS7: Bidirectional GaN Switches: Towards Reliability Standards & Field Deployment

Moderators: Davide Bisi, Renesas - Matteo Meneghini, University of Padova

Abstract: Thanks to its lateral architecture, GaN lends itself to monolithic integration. And the most useful example is the integration of two back-to-back transistors on the same chip, realizing the so-called bidirectional switch (BDS), capable of conducting and blocking current in both directions. GaN BDS are very useful in AC front-ends, to eliminate a power-conversion stage and a DC link capacitors, therefore attaining higher efficiency and smaller volume. GaN BDS is becoming increasingly popular with the industry demonstrating strong interest. In this workshop, we'll discuss the current state-of-the-art and the reliability standards required to make GaN BDS a success. In fact, because it's monolithically integrated, GaN BDS is subject to specific failure mechanisms not present in conventional unidirectional devices, and because of its bidirectional nature, conventional JEDEC qualification and reliability standards may need to be accompanied by new standards, specific for BDS. The sooner the reliability community realizes the importance of GaN BDS, the better for the world. Let's start the conversation.

Workshop WS8: Applications of Advanced Packaging Technology to Meet Reliability Challenges of High-Performance Datacenters

Moderators: Jyun-Lin Wu, TSMC - Keith Newman, AMD, Inc

Abstract: The exponential growth in compute demand for high-performance datacenters is driving increased reliability challenges. The rapid rise in performance, power, memory bandwidth, and networking bandwidth creates escalating reliability issues for Si, packaging, and system that are increasingly addressed by advanced 2.5D and 3D packaging technologies. These advanced packaging solutions reduce interconnect energies, decrease electrical parasitics, lower energy/bit, expand cooling performance, and improve system-level efficiencies.

Temperature-driven reliability failure mechanisms are particularly affected by the datacenter trend to pack more computing power into smaller spaces. Advanced packaging techniques, such as chiplets and interposers, enable more effective heat dissipation and temperature reduction by optimizing the physical layout of components and incorporating advanced materials that enhance thermal conductivity.

Advanced packaging solutions facilitate the rapid evolution of datacenters to keep pace with technological advancements and changing business needs, ensuring that they can deliver optimal performance, reliability, and service to end-users.

The workshop will discuss the key packaging developments required to meet the projected reliability demands of future datacenters.

Workshop WS9: Reliability for LLM Applications

Moderators: Preeti Chauhan, Google - Andrew Walton, Microsoft

Abstract: coming soon.

Workshop WS10: Reliability for AI Training Workloads

Moderators: Runsheng Wang, Peking University - Lining Zhang, Peking University

Abstract: This workshop explores reliability challenges with hardware and software used to accelerate AI training workloads, an increasing critical challenge for their deployment. AI tools, such as Large Language Models, while offering transformative potential, require significant software and hardware resources, amplifying the impact of failures and require a systematic approach to improving Reliability, Availability and Serviceability (RAS). Critically, this workshop will also address the significant hardware demands of AI tools such as LLMs. We will explore the challenges related to computational power, memory capacity, interconnects, specialized hardware requirements, cost, accessibility, system integration, and fault tolerance. By examining these intertwined software and hardware challenges, this workshop aims to identify key research directions and propose collaborative opportunities to advance the reliability of AI training workloads

Workshop WS11: Capturing Wear-Out and Failure Mechanisms in Silicon/Package Interactions

Moderators: Javier Diaz Fortuny, IMEC - Davide Apollo, Technoprobe

Abstract: The commercial semiconductor industry is rapidly advancing towards innovative packaging solutions, such as chiplets with advanced 3D die stacking and cutting-edge interconnect technologies. Furthermore, there is growing interest in deploying on-chip monitoring solutions to evaluate the reliability of chips during in-field operation, fulfilling lifetime requirements for chips and packages in critical sectors like automotive, aerospace, and Industry 4.0. In this context, offering reliability testing methodologies from chips to packages is gaining significant attention in today's dynamic mission-profile-driven market.

In this scenario, this workshop will explore how on-chip monitors can be employed to capture chip/package interactive failure mechanisms, enabling early detection of performance degradation and catastrophic failures. This workshop is ideal for professionals and researchers in the field of IC/package reliability, focusing on the development of novel monitoring solutions and providing a comprehensive understanding of the challenges and opportunities in the evolving landscape of commercial CMOS technology.

Bullet list discussion:

• IC and package reliability impact on mission critical applications in markets like automotive, aerospace or the industry 4.0.
• Chiplets, the new frontier of CMOS integration reliability.
• Reliability monitoring challenges and solutions from chip to packages to maintain yield and projected lifetime.
• Implantation of new predictive maintenance standards, such as the ISO 26262, for proactive and predictive maintenance of ICs and chiplet solutions.
• Advanced monitoring solutions of environmental phenomena in the CMOS industry: humidity, corrosion, high temperature and cryogenic environments.
• Design-for-test methods, architectures, and tools to facilitate the activation and observation of defects introduced at assembly level.
• Sensors and monitor IP’s to observe chip-to-package interaction effects.
• Test and repair mechanisms of interconnects and their impact on package-level reliability.

Workshop WS12: Laser and Electron-beam Based Techniques for Fault Localization in Semiconductor Devices

Moderators: Daniel Sullivan, EAG Labs - Greg Johnson,Zeiss Microscopy

Abstract: In this workshop we will present techniques for fault localization in semiconductor devices including Emission Microscopy (EMMI), Optical Beam Induced Resistance Change (OBIRCH), IR, and Thermal Reflectance (TR). These techniques utilize powering the devices while monitoring an output that indicates the location of leakage, opens, or shorts. This enables physical FA to be done in a small area of interest.

The limitations of each technique and the detection limits, resolution, and special setups will be discussed.