2025 Tutorials
Inside Program: Conference Program l Keynote Speakers l Tutorials
Workshops l Year in Review l Highlight Papers | Invited Speakers
Tutorial Program at a glance
List of Tutorials
Insights Into MOSFET Operation and Reliability Through 1/f Noise
Ruben Asanovski (imec)
This tutorial delves into understanding 1/f noise in the drain current of MOSFETs, emphasizing its role in device performance and reliability. We first explore the origins of 1/f noise and its relation to random telegraph noise (RTN). Next, we present state-of-the-art noise models, critically discussing their approximations. Finally, we showcase the potential of 1/f noise as a diagnostic tool for assessing dielectric quality, particularly for advanced logic technologies and quantum computing applications.
Dr. Ruben Asanovski earned a Ph.D. in Electronics Engineering from the University of Modena and Reggio Emilia in 2024. His research focuses on 1/f noise in state-of-the-art technologies down to cryogenic temperatures. He has received several awards during his studies, including the Best Student Paper Awards at IEDM 2022, EuroSOI-ULIS 2021, and INFOS 2023. In recognition of its expertise, he was invited to speak at the ICNF 2023 conference regarding 1/f noise at cryogenic temperatures. In 2024, he joined imec as a researcher in the DRE team.
Reliability of 3D NAND Flash Memory Devices
Luca Chiavarone (Micron)
The advent of 3D NAND flash memory has revolutionized data storage technology, offering significant improvements in density, performance, and cost-effectiveness compared to traditional planar NAND. However, the reliability of 3D NAND flash memory devices remains a critical concern, requiring deep investigation depending on the field application. This tutorial provides a comprehensive overview of the reliability challenges and solutions associated with 3D NAND flash memory devices.
Luca Chiavarone received the Ph.D. degree in physics from University of Bari, Italy, in 2000, with a thesis on the study of the optical properties of conjugated polymer thin films and the fabrication of electroluminescent organic devices. In 2000, he joined the Non-Volatile Memory Process Development Group, STMicroelectronics, Agrate Brianza, Italy, working on electric wafer sort and on the characterization, reliability and multilevel applications of Flash cells. In 2010 he joined Micron Technology, Vimercate, Italy, under Technology Development Group. He is currently SMTS - NAND Reliability, dealing with Flash memory physics, technology, and reliability modeling.
Reliability in Cutting-Edge Technologies for AI Applications
Ryan Lu (TSMC)
The rise of advanced silicon and packaging has increased the demand for HPC in AI applications, where any malfunction can be disruptive due to the many HPC units running simultaneously. Key factors include superior computing power efficiency, low DPPM, thermal management, and balanced packaging stress. Ensuring product robustness requires a thorough understanding of reliability. This tutorial covers transistor-level and package-level reliability. Additionally, DPPM management and future reliability challenges will be addressed in this AI era.
Dr. Ryan Lu is a Director in the TSMC Quality and Reliability organization, supervising reliability development and customer engagement across all silicon, specialty, and packaging technologies. He received his Ph.D. degree in Electrical Engineering from UCLA in 2004. From 2004 to 2013, he worked in Intel's QR organization. Since 2013, he has been a part of TSMC's QR organization, and he is currently supervising a reliability team of more than 300 engineers. Dr. Lu has more than 20 years of experience in the QR area and has authored or co-authored many conference and journal publications on reliability topics.
Accelerated Life Testing for Product Lifetime Extrapolation
Cher Ming Tan (Chang Gung University, Taiwan)
**Product lifetime** is a critical attribute of any technical product, as it directly influences the perceived value and long-term cost-effectiveness of the product. Meeting high product reliability standards often necessitates extensive testing to accurately predict the product's lifetime, a process that can be time-consuming. Consequently, accelerated life testing (ALT) is widely adopted to shorten the testing period. However, to ensure the reliability and accuracy of the lifetime prediction, a suitable extrapolation method must be selected based on the acceleration model. Unfortunately, identifying the most appropriate acceleration model for different failure mechanisms is a complex task, and conventional models commonly used in industry may not always be suitable. This tutorial will cover various acceleration models, discussing their applications and selection criteria for different types of failure mechanisms.
While acceleration models are primarily used to determine the acceleration factor, it is essential to use this factor effectively to perform accurate extrapolation. Traditionally, extrapolation is performed using a single reliability index, such as Mean Time to Failure (MTTF). However, a more comprehensive approach involves extrapolating the entire reliability function, a process known as two-dimensional extrapolation. This tutorial will provide an in-depth explanation of how to perform this two-dimensional extrapolation to ensure a more accurate and meaningful lifetime prediction.
For products requiring exceptionally high reliability, even accelerated life testing may not suffice due to the extended timeframes involved. In such cases, accelerated degradation testing (ADT) is increasingly employed. However, a common pitfall in ADT is the use of simple curve fitting methods to estimate failure times, which can lead to significant errors in lifetime prediction. This tutorial will present an example of proper extrapolation techniques in accelerated degradation testing to demonstrate best practices for accurate lifetime estimation.
Dr. Tan, a graduate from the University of Toronto, has vast expertise in electronic reliability (industry and academic), with over 400 publications and 14 books. He served at Nanyang Technological University (1996–2014) and now leads the Research Center on Reliability Sciences at Chang Gung University, Taiwan. An editor for journals like Scientific Reports and IEEE TDMR etc, he is also an IEEE Distinguished Lecturer. Recognized among the top 2% of scientists by Stanford University, he holds Fellow status with multiple international engineering organizations. He was elected the 1st President of the Taiwan Reliability Technology Association..
Ge-GST ePCM Reliability: An Intimate Interaction Between Material Properties and Device Operation
Andrea Redaelli (STMicroelectronics)
Among the emerging memories that can be integrated in the back end of the line, phase Change Memory (PCM) is emerged as one of the most interesting for embedded applications below 28nm node. The interplay between active material behavior and device operation is fundamental to mastering the technology. In the tutorial, the effect of the electrical operations done on the device are studied at the material level, clarifying the relationship between applied programming pulse, final microscopic phase and composition. The reliability of the technology is then discussed within this framework, highlighting some fundamental trade-offs between retention, cycling and retention after cycling. For the retention, the effect of Ge introduction on the crystallization incubation time will be discussed and, for endurance, the material aging effect. (i.e. compositional shift) is highlighted as a key mechanism to be mastered. Finally, the optimization done at process level to achieved automotive grade qualification will be discussed.
Andrea Redaelli received the Laurea and Ph.D. degrees in electronic engineering from the Politecnico di Milano, Italy, in 2003 and 2007 respectively. During the Ph.D., he worked on Phase Change Memories in the Department of Electrical and Electronic Engineering (Politecnico di Milano), collaborating with the Non-Volatile Memory Technology Development Group of STMicroelectronics, Agrate Brianza. From 2007, he joined STMicroelectronics working on advanced technologies for Non-Volatile memories. From 2008 to 2013 he worked as cell lead engineer on 45 and 26 nm PCM technology developments, firstly as a Numonyx employee and then joining Micron Technology. In the same years, Andrea cooperated with the Department of Electrical Engineering, Politecnico di Milano, in holding master classes on electronics and signal conditioning. His work areas included memory array architecture definition, design of test structures, process integration, cell operation modelling and cell electrical testing. He was also the coordinator of a European funded project under FP7 named PASTRY on low power PCM development. From 2014 to March 2020, Andrea worked on 3DXpointTM technologies, in charge of the cell development at the most advanced scaled nodes. Since April 2020, Andrea is a fellow in STMicroelectronics, leading the cell development of embedded PCM technologies and for AI applications. Andrea is author and co-author of more than 70 papers and more than 140 US patents, resulting in a h-index of 32 according with google scholar.
Dielectric Breakdown and Resistive Switching – Two Sides of One Coin
Rainer Waser (Peter Grunberg Institut)
Depending on the dielectric material and geometry, several dielectric breakdown mechanisms can be distinguished. In their final phase, they all lead to a thermal runaway. The initial phase is a completely electronic process, immediately followed by ion movement. This is identical to the electroforming process in resistive switching. To prevent a permanent destructive breakdown, the current during this process must be limited either by a series resistor or an ultra-fast current control.
Rainer Waser received his PhD in physical chemistry at the University of Darmstadt in 1984, and worked at the Philips Research Laboratory, Aachen, until he was appointed Professor at the faculty for Electrical Engineering and Information Technology of the RWTH Aachen University in 1992 and director of the Institute for Electronic Materials at the Forschungszentrum Jülich, in 1997. In 2007, he has been co-founder of the Jülich-Aachen Research Alliance, section Fundamentals of Future Information Technology (JARA-FIT). In 2014, he received the Leibniz Prize of the German national science foundation (DFG) for his work on the phenomenon of redox-based resistive switching.
Future Automotive Mission Profiles for the Era of Software-defined Vehicles
Oliver Senftleben (BMW)
The demand for automotive mission profiles enabling a detailed reliability assessment for all utilized semiconductor and device technologies is continuously increasing due to new lifetime requirements for zonal architectures and fully electric autonomous software-defined vehicles (SDV).
The tutorial will focus on these new challenges and will present a new hierarchical approach to define EMPs for various applications, installation spaces and climate zones wrt. temperature, temperature swing and humidity.
Oliver Senftleben holds a master's degree in physics and a PhD in electrical engineering. Since 2011 he has been working as a Senior Technical Expert for Semiconductor Technologies at AUDI AG and is currently responsible for wide band gap power devices and mission profiles within the department for Semiconductor Strategy at BMW Group in Munich.
As a part of his responsibilities he is representing BMW towards the Automotive Electronics Council, is member of the ECPE AQG 324, German VDA 210-200 (Hardware Delta-Qualification) and German VDE 5.7 working group on Extended Mission Profiles.
ESD and Reliability Worlds: Analogies and Differences
Lorenzo Cerati (ST Microelectronics)
Reliability assessment of Integrated Circuits and the definition of their robustness when exposed to Electrostatic Discharge (ESD) events show many commonalities but also meaningful differences in the adopted stress methodologies and theoretical modelling approaches. This tutorial will first focus on the ESD stress testing methods and on the international standards (Human Body Model, Charged Device Model…), which define the basic rules of this field. Differences between device-level and system-level assessments will be analyzed to determine the actual threat that any IC may be exposed to during its entire lifetime. The basic approaches to implement an effective ESD protection network will be presented, identifying the key physical and electrical parameters. Finally, the various characterization techniques adopted by ESD engineers will be shown, highlighting the numerous analogies with the reliability investigations and the also the important differences between the two worlds. Degradation mechanisms and physical failures peculiar for each of these fields will be discussed.
Lorenzo Cerati is reliability, ESD and CPI (Chip-Package Interaction) Technical Director for Smart Power Technologies and Fellow of the Technical Staff at STMicroelectronics. Lorenzo received his M.Sc. degree in telecommunication engineering at the "Politecnico di Milano" Technical University in 1998, discussing a thesis on a CdZnTe cross-connect for optical networks. Since 2000, Lorenzo has been working in STMicroelectronics, starting as ESD protections development engineer for Smart power technologies (BCD). Lorenzo has led the group responsible for ESD protections development, Latch-up immunity and bipolar parasitic analysis in BCD processes for about 15 years and represented STMicroelectronics in the ESDA standardization committees, including HBM, CDM and TLP, where he also acted as vice-chairman. From 2016 to 2023 he served as member of the ESDA Technical and Advisory Support Committee (TAS), ESDA Board of Directors and acted as co-chair of the Standards BU. Since 2022 Lorenzo has been leading the team responsible for the qualification of BCD technologies in STMicroelectronics.
Lorenzo served multiple times as a member of the ESREF, ICICDT, IRPS, IEW, and EOS/ESD Symposium Technical Program Committees and authored several papers on ESD and EDA topics. Lorenzo was General Chair at the 2020 EOS/ESD symposium and chaired the ESD&LU session at the 2024 IRPS.
Corrosion in µ-electronic Devices : An Overview From FE Manufacturing to Product-life & Reliability
Lucile Broussous (ST Microelectronics)
In this tutorial, first general concepts will be provided about Corrosion, based on elemental "corrosion Triangle", then focus will be done on fundamentals properties of metals and materials used in microelectronics. First part will focus on corrosion in Front End and Backend Manucaturing. Then Corrosion mechanisms in product life and reliability risks will be explored for different technologies. At least a focus will be done on Devices robustness assessments and Corrosion prevention.
Dr. Lucile Broussous, received a PhD in physical-chemistry in 1999, at the University of Montpellier. She joined STMicroelectronics in 2001 as an R&D process engineer.
From 2001 to 2018, she acquired a strong experience on surface preparation, cleaning, materials for interconnections. In 2018, she joined the Chip to Package Interaction team, and enlarged her technical knowledge to Assembly processes and Reliability. She was involved in the qualification of Image sensors and CMOS technologies for different applications and missions profiles.
Collaboration with Universities focused on metals corrosion in solution, contamination, porous dielectrics porosity measurements, with a specific focus on product reliability.
Fundamentals of Circuit Aging: From Devices to Test Chips to Products
Christopher S. Chen (Intel)
This tutorial will provide an overview of how transistor aging affects circuit performance and reliability. We will begin with an overview of various device aging mechanisms and demonstrate how they manifest at the circuit level. Next, we will cover how these aging mechanisms are characterized using silicon test structures and modeled in circuit simulations. Finally, we will discuss how circuit aging can be measured on test chips to help predict the reliability of semiconductor products.
Christopher Chen is a circuit reliability engineer with Intel. He holds a B.S. in EECS from UC Berkeley and an M.S. in EE from UCLA. He began his career as a device characterization engineer with Altera and joined Intel in 2015 via acquisition. During his 18 years with Altera and Intel, Chris has held various roles focusing on foundry interface, technology development, device engineering, parametric test, and transistor reliability. Throughout this time, he has consistently worked on the design and characterization of test structures for assessing technology performance, reliability, and variability. Chris has published 15 papers and holds 3 patents.
CMOS RF Reliability: Methodology and Modeling
Xavier Garros (CEA Leti)
The growing need for connectivity has significantly driven the RF component market forward. Consequently, in CMOS technologies, RF functions have been added to purely digital circuits to enable communication functions. The issue is that transistors were not originally designed for RF but solely for digital applications. This raises significant reliability issues for several reasons: (1) the operational mission profile of an RF transistor is often much more demanding than that of a digital transistor, and (2) certain aging mechanisms either emerge or are altered at high frequencies, requiring aging characterization directly under RF stress conditions and a reevaluation of reliability models to account for high-frequency specifics. In this tutorial, we propose to study in detail the reliability of devices under RF stress conditions. First, we will address the challenges of RF aging characterization at the wafer level, offering a clear methodology to achieve robust and relevant results. Then, we will discuss the various possible approaches to model the reliability of RF components. Finally, the impact of high frequencies on degradation mechanisms will be examined, with a particular focus on oxide breakdown.
Xavier Garros is a senior scientist in the Electrical Characterization Laboratory of the CEA-LETI. He received his Ph.D. from the University of Marseille, France (2004), on the physics and electrical properties of High-K dielectrics. He has a deep knowledge in electrical characterization, physics and modeling of the reliability concerns in advanced technologies (Bulk, FDSOI, Nanowire). Recently he also addresses other research fields like circuit and RF reliability. He supervised and is supervising 9 thesis so far. He wrote, as author and co-author, 3 patents and more than 100 papers in international conferences and journals about CMOS reliability physics. He is also involved in the program committee of famous international conferences in that field (IEDM, IRPS, SISC..).
CMOS Device Reliability: Challenges and Physics Fundamentals
Luca Larcher and Gaurav Thareja (Applied Materials)
We will discuss the advanced logic technology roadmap and device reliability constraints for both Front-End-of-Line (FEOL) and Back-End-of-Line (BEOL) processes. Then we will delve into the physics of device reliability from an atomic defect perspective, focusing on defect trapping and generation, and covering key reliability issues such as Bias Temperature Instability (BTI), Self-Heating Effects (SHE), Breakdown/Time-Dependent Dielectric Breakdown (BD/TDDB), and Electromigration (EM), with a focus on BD characterization and modeling. Additionally, we will discuss the challenges in characterization, including the transition from accelerated tests to real operating conditions and the shift from simple test vehicles to complex 3D devices. We will emphasize the role of physical modeling, with a focus on connecting process steps to material properties and predicting device and circuit behavior based on these properties.
Luca Larcher graduated in Electronic Engineering from the University of Padova, Italy, in 1998. He received his Ph.D. degree in “Information Engineering” from the University of Modena and Reggio Emilia in 2002. He was appointed as Assistance Professor in 2001, Associate Professor in 2005, and Full Professor of Electronics in 2017. In 2017, he co-founded a startup (MDLSoft Inc), which was acquired by Applied Materials in 2019. From April 1st 2019 he is with Applied Materials, as a Managing Director leading the Ginestra simulation S/W team. His current research interests include the modeling and characterization of electron devices with focus on physical mechanisms governing charge transport and material degradation. In the past, he worked also on RFIC and energy harvesting circuit design. He authored and co-authored one book and three book chapters, and more than 300 technical papers published on international journals and proceedings of international conferences (H factor 54). He has joined the technical and executive committees of the IEEE-IEDM (2006-2007, 2013-2015), IEEE-IRPS (2011-2012, 2017-2019) and IIRW (2013-2018, he served as General Chair in 2018).
Gaurav Thareja is Head of Logic and Memory Process Integration in the Metals Deposition Products division of the Semiconductor Products Group at Applied Materials, Santa Clara, USA. With a prolific career, he has made significant contributions to semiconductor device processes and materials technology. He is a recognized inventor, holding 40+ US patents, and having authored more than 30 publications and many invited talks. He received PhD in Electrical Engineering from Stanford University and has over 15 years of experience in the semiconductor industry, previously with an AI startup in bay area (Founding team and COO), High performance logic for 7/3/2nm nodes at Intel Process Technology Development in Hillsboro Oregon (Process Integration Lead), Transistor Reliability CAD at Texas Instruments (Design engineer) and ROM circuit design (Intern) at ST Microelectronics.
Reliability of SiC Power Semiconductors
Paul Salmen (Infineon)
This tutorial will give an overview on the field of reliability of SiC power semiconductors. The first part will cover gate oxide related fails due to extrinsic/intrinsic defects and the SiC specific failure mechanism gate switching instability. In the next section, the tutorial will focus on everything related to the edge termination, especially humidity induced degradation of SiC devices. The last part will then deal with degradation mechanisms related to the bulk SiC crystal. Here, degradation of electrical parameters (namely bipolar degradation) as well as thermomechanical stress like power cycling are driven by the properties of the SiC crystal. Where available, the tutorial will also show which topics are addressed by already published JEDEC documents.
Dr. Paul Salmen is working currently as principal for reliability of SiC power semiconductors in the division green industrial power at Infineon technologies. He received his PhD in physics at the TU Dortmund university in 2017 and is, since then, working at Infineon technologies on SiC reliability. His work focuses on understanding the degradation mechanisms of SiC power devices and their chip-package-interaction with a focus on modules.
Microcircuit Reliability Management in Space ESA Missions: From System Perspectives Down to the EEE Component
Florian Moliere (European Space Agency)
The aim of this tutorial is to present the microcircuit reliability activities set up in Space programs to guarantee the success of the space missions from the spacecraft system level down to the EEE component.
Dr. Florian Moliere is EEE expert at European Space Agency (ESA/ESTEC). He acts as both project support for earth-observation, science, human robotic and robotic exploration mission programs and microcircuit specialist. He holds both an Engineering degree in Electronics from ISEN -Toulon in 2007 and a Ph.D in Microelectronics from the University of Aix-Marseille in 2011. Moreover, Florian has 17 years of experience in aeronautics and space industry within Airbus Group (formerly EADS) in Paris (France) as EEE technologist and reliability engineer, and within Airbus Defence and Space in Friedrichshafen (Germany) as EEE engineer for project support and Product Assurance Manager.
GaN Device Reliability
Brian Rummel (Sandia)
Coming soon.
Brian Rummel is a senior member of technical staff at Sandia National Laboratories in Albuquerque, NM. His research group at Sandia studies wide bandgap materials like gallium nitride & silicon carbide as they pertain to power electronics. Brian's primary research focus is reliability physics semiconductor in discrete power devices, as well as defect analysis in wide bandgap systems. He also has experience in piezoelectric materials and semiconductor device processing. Brian received his Ph.D. in nanoscience & microsystems engineering at the University of New Mexico.
Other Confirmed Tutorial Speakers (Bios and abstracts coming soon!)
Myunggil Kang (Samsung), Reliability in advanced transistor technologies
Adrian Vaisman Chasin (imec), IGZO reliability
Mayank Shrivastava (Indian Institute of Science), 2D Material’s Technological Progress and Reliability Challenges for Next-gen Nanoelectronics & Quantum Technologies
Pierre Maillard (AMD), Radiation Effects and Mitigation Strategies in FPGAs and SoCs for Terrestrial and Space Systems