2024 Tutorials

Inside Program: Conference Program l Keynote Speakers l Tutorials
Workshops l Year in Review l Highlight Papers | Invited Speakers


List of Tutorials



Insights Into MOSFET Operation and Reliability Through 1/f Noise

Ruben Asanovski (imec)

This tutorial delves into understanding 1/f noise in the drain current of MOSFETs, emphasizing its role in device performance and reliability. We first explore the origins of 1/f noise and its relation to random telegraph noise (RTN). Next, we present state-of-the-art noise models, critically discussing their approximations. Finally, we showcase the potential of 1/f noise as a diagnostic tool for assessing dielectric quality, particularly for advanced logic technologies and quantum computing applications.


Dr. Ruben Asanovski earned a Ph.D. in Electronics Engineering from the University of Modena and Reggio Emilia in 2024. His research focuses on 1/f noise in state-of-the-art technologies down to cryogenic temperatures. He has received several awards during his studies, including the Best Student Paper Awards at IEDM 2022, EuroSOI-ULIS 2021, and INFOS 2023. In recognition of its expertise, he was invited to speak at the ICNF 2023 conference regarding 1/f noise at cryogenic temperatures. In 2024, he joined imec as a researcher in the DRE team.



Reliability of 3D NAND Flash Memory Devices

Luca Chiavarone (Micron)

The advent of 3D NAND flash memory has revolutionized data storage technology, offering significant improvements in density, performance, and cost-effectiveness compared to traditional planar NAND. However, the reliability of 3D NAND flash memory devices remains a critical concern, requiring deep investigation depending on the field application. This tutorial provides a comprehensive overview of the reliability challenges and solutions associated with 3D NAND flash memory devices. It begins with a brief overview of the transition from planar to three-dimensional architectures, highlighting how this shift has altered the impact of previously known reliability issues and introduced new challenges. A detailed comparison between 3D NAND Floating Gate (FG) and Charge Trap (CT) technologies will be provided, outlining the pros and cons of each. Furthermore, participants will gain insights into the latest error correction techniques, and design strategies that enhance the reliability of 3D NAND flash memory. Through detailed explanations and practical examples, this tutorial aims to equip attendees with the knowledge needed to address reliability issues and optimize the performance of 3D NAND flash memory in various applications.


Luca Chiavarone bio coming soon.



Reliability in Cutting-Edge Technologies for AI Applications

Ryan Lu (TSMC)

The rise of advanced silicon and packaging has increased the demand for HPC in AI applications, where any malfunction can be disruptive due to the many HPC units running simultaneously. Key factors include superior computing power efficiency, low DPPM, thermal management, and balanced packaging stress. Ensuring product robustness requires a thorough understanding of reliability. This tutorial covers transistor-level and package-level reliability. Additionally, DPPM management and future reliability challenges will be addressed in this AI era.


Dr. Ryan Lu is a Director in the TSMC Quality and Reliability organization, supervising reliability development and customer engagement across all silicon, specialty, and packaging technologies. He received his Ph.D. degree in Electrical Engineering from UCLA in 2004. From 2004 to 2013, he worked in Intel's QR organization. Since 2013, he has been a part of TSMC's QR organization, and he is currently supervising a reliability team of more than 300 engineers. Dr. Lu has more than 20 years of experience in the QR area and has authored or co-authored many conference and journal publications on reliability topics.


Accelerated Life Testing for Product Lifetime Extrapolation

Cher Min Tan (Chang Gung University, Taiwan)

**Product lifetime** is a critical attribute of any technical product, as it directly influences the perceived value and long-term cost-effectiveness of the product. Meeting high product reliability standards often necessitates extensive testing to accurately predict the product's lifetime, a process that can be time-consuming. Consequently, accelerated life testing (ALT) is widely adopted to shorten the testing period. However, to ensure the reliability and accuracy of the lifetime prediction, a suitable extrapolation method must be selected based on the acceleration model. Unfortunately, identifying the most appropriate acceleration model for different failure mechanisms is a complex task, and conventional models commonly used in industry may not always be suitable. This tutorial will cover various acceleration models, discussing their applications and selection criteria for different types of failure mechanisms.

While acceleration models are primarily used to determine the acceleration factor, it is essential to use this factor effectively to perform accurate extrapolation. Traditionally, extrapolation is performed using a single reliability index, such as Mean Time to Failure (MTTF). However, a more comprehensive approach involves extrapolating the entire reliability function, a process known as two-dimensional extrapolation. This tutorial will provide an in-depth explanation of how to perform this two-dimensional extrapolation to ensure a more accurate and meaningful lifetime prediction.

For products requiring exceptionally high reliability, even accelerated life testing may not suffice due to the extended timeframes involved. In such cases, accelerated degradation testing (ADT) is increasingly employed. However, a common pitfall in ADT is the use of simple curve fitting methods to estimate failure times, which can lead to significant errors in lifetime prediction. This tutorial will present an example of proper extrapolation techniques in accelerated degradation testing to demonstrate best practices for accurate lifetime estimation.



Cher Min Tan bio coming soon.