Inside Program: Conference Program l Keynote Speakers l Tutorials
Workshops l Year in Review l Highlighted Paper

*Workshops available to on-site attendees only

March 28th (Tuesday)

6:00 -7:30 PM: Workshop Reception with full food service

7:30-8:30 PM: 1st Session

8:45-9:45 PM： 2nd Session

Chair: PJ Liao (TSMC), Co-chair: Bonnie Weir (Broadcom)

Abstract: Moore’s law forecasts continuous technology scaling to improve power, performance, area, and cost. Ground-rule scaling from processing modules, tools, material properties, etc., has been adopted to achieve the aforementioned performance merits. Those bring reliability challenges if the same maximum voltage (Vmax) is sustained for product usage at a given operation lifetime. For example, BTI/SILC and hot carrier injection on transistors with thinner gate dielectrics and dimensional scaling, VBD/TDDB on inter/intra-metal dielectric layers and ILD Cu/low-k dielectric systems with minimum-space scaling, etc. Facing continued demands of overall performance scaling, thorough consideration of raised reliability challenges across FEOL, MEOL to BEOL is required. Solutions from new reliability modeling or technology DTCO are also imperative to unleash technology value and bring opportunities in reliability.

Chair: Ivan Ciofi (IMEC), Co-chair: Rahim Kasim (Intel)

Abstract: Innovation in BEOL materials is key to keeping the pace with Moore’s law and, at the same time, meeting the expected performance and reliability requirements. Alternative metals to Cu are currently being investigated to mitigate the degradation of interconnect RC and reliability with dimensional scaling. Material screening is typically based on figures of merit such as low mean free path times bulk resistivity, high cohesive energy, better oxidation resistance and high melting point. Ru, Mo, Co and W are the most popular candidates, as they are less disruptive options for the semiconductor industry. Such metals exhibit superior resilience to electromigration failures and can tolerate current densities way above what logic and memory designs require for future technology nodes. On the other hand, high currents cause high joule heating, which can induce early failures in the upper (or connected) Cu metal layers (e.g. electromigration, thermomigration) or raise junction temperature. These reliability aspects get further exacerbated by the possible presence of air gaps, which hinder thermal dissipation. Thermo-mechanical failures should be also considered. In this workshop, we would like to invite experts to brainstorm on JMax criteria for alternative metals, focusing on both integrity failures and operation failures.

Chair: Matthew Hogan (Siemens EDA), Co-chair: Nate Peachey (Qorvo), Lorenzo Cerati (ST)

Abstract: Reliability challenges at all process nodes continue to drive the need for greater advances in verification methodologies. ESD and latch-up are of particular concern and great interest. Visual inspection and manual methods do not provide a repeatable or deterministic mechanism to assure consistent reliability verification coverage. Automated reliability verification methods need to be used to overcome these limitations, especially for larger designs. Specifically, for ESD and latch-up, the question becomes one of coverage, design margin and applicability for specific design styles. This workshop explores the varied needs of different IC design types, sizes, and today’s EDA tool suitability. Are EDA verification tools sufficient for today’s designs? What gaps & opportunities are there? Please join us as we explore this topic.

Chair: Jin-Woo (Samsung Electronics), Co-chair: Thomas Vogelsang (Rambus)

Abstract: As system performance advances and memory capacity scales, 3D stacking of DRAM introduces promising opportunities. For example, stacking technology could be found in various applications such as high bandwidth memory (HBM) as well as heterogeneous integrations; last level cache (LLC) DRAM and DRAM-Logic stacking. In this workshop, we will discuss reliability concerns such as moisture ingress, thermomechanical stress, electromigration, Cu diffusion, dielectric breakdown, noise, etc. with emphasis on their influence on DRAM behavior.

Chair: Dan Sullivan (EAG), Co-chair: John Moskito (EAG)

Abstract: The progress of technology keeps making things smaller.  We still need to work with them and get FA done.  Down to 3 micron gates now.  What can be done with the modern tools?  What approaches need to change to address this new mode?

Chair: Jacopo Franco (IMEC), Co-chair: Andreas Kerber (Intel)

Abstract: In order to sustain the traditional CMOS scaling trends in terms of enhanced performance, increased transistor density and reduced power dissipation, the device integration complexity has dramatically increased in the last decades, with the introduction of High-K Metal Gates, multi-Vth offering by Work Function Metal engineering in the RMG module, and finFET device architecture. The transition from finFET to Gate-All-Around (GAA) devices (often referred to as Nanosheets, Nanoribbons or Multi-Bridge Channel FETs) is expected at the 2nm node in 2024/2025. Further disruptive innovations in both FEOL and BEOL will be needed for scaling beyond the 2nm node. Frontrunner options include: transition to Forksheet device architecture for reduced n-to-p spacing, Complementary-FET architectures (CFETs) with stacked n- and p- channel devices for minimal Logic Gate footprint, 2D channels for ultimate electrostatics control, back-side power distribution, buried power rails and new metalization materials (Ruthenium) and fabrication methodologies (subtractive metallization/direct metal etch) for interconnect performance enhancement. Each of these innovations brings along serious integration challenges and potential reliability concerns. Traditional aging mechanisms (Bias Temperature Instabilities, Hot Carrier Degradation, Time-Dependent Dielectric Breakdown, Self-Heating Effects) might be exacerbated by new device architectures (e.g., lack of substrate connection in GAA’s) and their fabrication flows (e.g., new materials, reduced process thermal budgets), while novel degradation mechanisms specifically related to the new integration solutions might potentially come up as topmost concerns. The discussion in this workshop will revolve around these topics, with the goal of formulating a list of priorities to focus the efforts of the reliability research community in view of the upcoming device technology innovations.

Chair: Don Gajewski (Wolfspeed), Co-chair: Paul Salmen (Infineon)

Abstract: The demand is rapidly increasing for SiC MOSFETs and diodes for electrified vehicle (EV) charging and traction applications. These applications employ a high quantity of large-area die per system while demanding high system-level reliability under aggressive electrical and environmental operating conditions. In addition, some of the SiC device failure mechanisms can be more impactful than they are in Si or have no direct analog in Sidevices. While single-event burn-out (due to terrestrial neutrons) and gate oxide wear-out are similar between SiC and Si, bias-temperature instability (BTI) can be more prominent in SiC, due to the higher density of gate oxide interface and near-interface charge traps. In addition, SiC MOSFETs are susceptible to bipolar degradation (increased on-resistance and possibly leakage), due to the conversion of basal plane dislocations (BPDs) to stacking faults under the influence of electron-hole recombination, which occurs in third quadrant operation. This situation demands thorough and novel device reliability characterization and quantification. In this workshop, we will present talking points to stimulate lively discussion about these critical topics.

Chair: Fen Chen (GM Cruise), Co-chair: Xiaojin Wei (Rivian)

Abstract: Artificial intelligence (AI) and Machine Learning (ML) are becoming pervasive in today’s applications adopted by autonomous vehicles (AV), healthcare, aerospace, cybersecurity, E-commerce, education, etc. Reliability, Availability, and Serviceability are key to AI/ML Compute operations. Because of the relatively high costs and the mission-critical requirement of using AI/ML Computes, a holistic approach must be implemented to ensure the reliability and robustness of the AI/ML Computes. For autonomous driving (AD) usage, any hardware performance degradation and failures including soft failures due to performance regression and intermittent malfunctions could trigger a fatal accident. Therefore, an AV Compute system must be able to be functional with top performance and must always respond faster than the human driver to guarantee AD safety. In this workshop panel discussion, we will explore AI/ML Compute reliability specifications and requirements for both data center and automotive usages such as the new chip-level reliability target vs the system-level reliability target considering the assembly of many parallel components/chips in the AI/ML Compute systems, safety correlated reliability requirements, thermal management/power consumption impact on reliability, extreme environmental operation requirements, automotive grade EMC/ESD requirements, component manufacturing quality/process variation control challenges, and AECQ requirement revisit for autonomous driving applications.

Chair: Sundarshan Rangaraj (Google), Co-chair: Swanand Vaidya (Google)

Abstract: Consumer electronics have evolved rapidly over the past decade. Notable examples range from what we see in our daily lives like smartphones, tablets, wearables to IOT devices and extending into frontier applications like augmented and virtual reality hardware. A plethora of new applications pose unique demands on reliability of integrated circuits' silicon and package. Using more conventional standards based qualification strategies may lead to over or under design that can result in added cost or risk of failures in customers hands respectively. Working backwards from the customers and intended use cases allows manufacturers to design components and subsystems that meet reliability goals at optimal cost and time to market. This approach is the bedrock of knowledge based qualification plans. This workshop will bring together experts across the reliability community to delve deeper into this area.

Chair: Chundong Liang (AWS), Co-chair: Enrique Carrion (Google cloud)

Abstract: Nowadays data centers use millions of server chips that run 24 x 7 with various applications, workloads, and maintenance.The growth of both the scale of data centers and the increase in chip complexity has increased the visibility of all failure modes. This workshop is about the survey discussion of key semiconductor quality and reliability failures for today's data centers. 

Chair: paologargini1@gmail.com (IRDS chairman), linda_wilson1225@ieee.org (IEEE)

Abstract: Systems, Architectures, and Device Capabilities future considerations and impact:  Join a panel discussion with IRDS thought leaders on these subjects...