2024 Tutorials

Registered attendees may access the tutorial slides on the Underline site.

Tutorial Program at a glance

List of Tutorials

TUT 1: Reliability Aspects of Nanowire, Nanosheet and Forksheet Devices

Eric Bury (imec)

In this talk, we will cover the front-end reliability aspects and challenges that come along the imminent shift towards Gate-All-Around based MOSFETs architectures in cutting-edgelogic technologies. Additionally, we explore innovative architectural derivatives, like Forksheets FETs, towards continued logic cell downscaling. The tutorial extends to the distinctive integration challenges posed by these devices, and we will examine their impact on both time-zero and time-dependent performance, including dielectric walls for N-to-P separation and device substrate isolation.

Erik Bury received the B.Sc., M.Sc. and PhD degrees in Electronic Engineering from the Katholieke Universiteit Leuven - Belgium, in 2009, 2011 and 2016 respectively. He is currently electrical and functional test (EFT) team leader and principal member of technical staff within the advanced reliability and robustness department of imec. His main research interests involve device self-heating effects, channel hot carrier degradation and bias temperature instabilities. He received the IPFA Best Paper award (in reliability) in 2014 and IRPS Best Paper award in 2022. He is serving or served as a technical program committee member for ESSDERC, IPFA and IRPS.

TUT 2: GaN Power Device Technology and Reliability

Davide Bisi (Transphorm Inc.)

Thanks to its superior switching properties, GaN is penetrating several power applications resulting in highest efficiency and system miniaturization. In this seminar, we’ll review the key device technologies (e-mode and cascode) and discuss their trade-offs between performance and reliability. We will show how to achieve high voltage rating up to 1200V and short-circuit capability up to 5 microseconds. The main topologies and applications will be presented, discussing good practices to use GaN fast, but reliably.

Davide Bisi is a Senior Member of Technical Staff with Transphorm Inc. He is leading multiple R&D projects on advanced GaN materials and devices.

He has more than 10 years of experience on GaN. In 2015, he received a PhD degree from the University of Padova, Italy, where he conducted highly cited research on the dynamic properties of GaN devices. After his degree, he visited the University of California, Santa Barbara, further expanding his expertise on GaN device physics.

Davide joined Transphorm in 2016, contributing to the demonstration of short-circuit capability for GaN devices, 1200-V rating, and bidirectional switches.

Dr. Bisi has co-authored more than 50 peer-reviewed publications and has been awarded 4 Best Paper Awards and 6 Patents. He is currently the vice-chair of the GaN technical committee for the IEEE IRPS Conference.

TUT 3: Introduction to Statistics for Reliability

Kristof Croes (imec)

This tutorial covers 6 main topics:

  • Basic data types used in the field of reliability

  • Basic distribution functions and its application

  • Main lifetime models, their use and their properties

  • Basic fitting methods used in fitting reliability data to the most suited distribution and lifetime model

  • Basic ways to display distributions, lifetime models and their fits

  • Some more advanced statistical models to account for variability issues in advanced devices

Kristof Croes has an MSc in physics and biostatistics. He obtained a PhD concerning the development of statistical techniques for planning reliability experiments. For seven years, he was product and application manager of the package level reliability products of the Singaporean based company Chiron holdings. Beginning 2007, he went back to research, where he is currently scientific director working on the reliability of advanced devices, interconnects and packages. Kristof was an (invited/tutorial) speaker at several leading-edge semi-conductor conferences [IRPS, IEDM, IITC, IPFA, …]. He also (co)authored more than 100 articles in the field of reliability.

TUT 4: Threshold-Voltage Instability in SiC MOSFETs

Aivars Lelis (ARL)

This tutorial will cover basic mechanisms, differentiating between transient and permanent shifts in threshold voltage (VT), and discussing the impact of such instability on device reliability and performance. Specific topics will include: VT shift versus VT drift and hysteresis, and how to measure both static and dynamic instability; dependence on measurement speed, bias, and temperature; degradation and VT shift; bias-temperature stress degradation; gate-switching (AC) stress degradation; dynamic on-state resistance; and other related effects and analysis.

Aivars Lelis has led the Power Device Reliability Physics Team at ARL over the past twenty years, with a focus on the device reliability physics of SiC MOSFETs for high-voltage, high-temperature, high-efficiency power conversion and conditioning for advanced Army systems. He received the ARL Sensors and Electron Devices Director’s Award in 2019 for his contributions to the development of SiC power-device technology, and the 2020 ARL Seminal Work award for his SiC MOSFET reliability work. He received his Ph. D. from the University of Maryland and has co-authored over 100 journal publications. From 2006 through 2019 Dr. Lelis led an annual SiC MOS workshop, and has served on the technical committees of various SiC conferences, including IRPS, ICSCRM, and WiPDA.

TUT 5: Reliability of RRAM Technology in the Context of Neuromorphic Applications

Cristian Zambelli (The University of Ferrara)

Resistive switching memory (RRAM) technology is a promising resource in the landscape of neuromorphic computing applications. In fact, RRAM can provide a convenient primitive for matrix-vector multiplication with a strong impact on the acceleration of Deep Learning. However, RRAM is affected by intrinsic conductance variations which might cause short- and long-term reliability issues. This tutorial will present a multiscale approach, ranging from the device to the circuit level, to mitigate those issues for accelerator design.

Cristian Zambelli received the M.Sc. and the Ph.D. degrees in Electronics Engineering and Engineering Science from the University of Ferrara, Ferrara, Italy, in 2008 and 2012, respectively. In 2015, he joined the Department of Engineering at the same institution where currently holds an Associate Professor position. His current research interests include electrical characterization and reliability modeling at an array level of different non-volatile memory technologies such as Flash (Planar and 3D), and emerging concepts such as Resistive RAM (RRAM). He is also interested in the development of cross-layer techniques for memory reliability/performance trade-off exploitation in Solid State Drives (SSDs), Neuromorphic computing accelerators, and storage in High-Performance Computing scenarios.

TUT 7: Understanding and Modeling Time-Dependent Dielectric Breakdown

Robin Degraeve (imec)

This tutorial aims at presenting an overview of degradation phenomena that lead to dielectric breakdown. We discuss how dielectric degradation can be observed and show possible consequences for device operation. An important aspect of TDDB is a correct description of its statistics, that can be derived from individual defect generation dynamics. We look at modeling approaches and ways of calculating the time-to-breakdown. We also discuss differences and similarities of breakdown in FEOL, MEOL and BEOL.

Robin Degraeve received M.Sc. and Ph.D. degree from Ghent and Leuven University, Belgium, resp. In 1992, he joined the CMOS Reliability Group at imec in Belgium, where he worked on dielectric breakdown phenomena and various electrical characterization techniques of dielectric defects. His interests are in the physics of reliability phenomena in CMOS technology, as well as in the reliability and modelling of future memory concepts. From 2010 on, he worked on the modelling of filamentary Resistive RAM, the conduction behaviour in poly-Si channels for vertical SONOS devices, and ovonic threshold switching. Currently, he is also exploring the use of reliability mechanisms and novel device physics for alternative computing paradigms with applications in machine learning and security.

TUT 6: Defect Localization Methods for Device Characterization and Yield Management

Greg Johnson (Carl Zeiss Microscopy)

Defect localization is key to device improvement, yield management, and reliability fail characterization.  How do you isolate defects when your fails are blowouts? How does one choose an FA technique form the alphabet soup of techniques? This tutorial will offer an overview of a wide variety of electron, ion, and laser-based fault isolation techniques from decades of fab experience and cutting-edge technique development in microscopy development. 

Greg Johnson has a BS degree from Virginia Tech and performed some graduate research at the University of Florida.  At IBM’s Packaging Development Laboratory, he honed his FA skills in packaging, and was soon named an Inventor on 19 US Patents in greensheet formulation and sintering.  Then, at IBM’s Semiconductor Research and Development Center, he was either the lead or sole FA engineer for FEOL defect localization across seven, successful, bulk technology node qualifications. And one in SOI. Now at Carl Zeiss Microscopy, he is developing applications in electron and ion microscopy for the semiconductor industry.

TUT 8: TCAD for Reliability

Karim El Sayed (Synopsys)

Technology Computer Aided Design (TCAD) tools are well established for modeling semiconductor fabrication processes, and device operations. This tutorial provides an overview how TCAD can is for modelling of various reliability issues, including mechanical stresses introduced during manufacturing process or device operations, Electrostatic Discharge (ESD), latch up/junction breakdown, Hot Carrier Degradation (HCD) and Negative Temperature Bias Instability (NTBI) and Time Dependent Dielectric Breakdown (TDDB), modeling of charge loss mechanics in 3D NAND memories, and others.

Karim El Sayed received the Dipl. Ing. And the Ph.D. degree in physics from the University of Frankfurt, Frankfurt, Germany. He worked as a Post-Doctoral Fellow at the Micro- and Nanotechnology Research Center of the Danish Technical University, Lyngby, Denmark and as Postdoctoral Fellow, in the Physics Department of the University of Florida, Gainesville, before joining Integrated Systems Engineering. Where he worked as a TCAD Applications Engineer. Dr. El Sayed today leads the Synopsys TCAD field application engineering team with the focus of customer support, product engineering and application development

TUT 9: Reliability of Nanoelectronics based on Two-Dimensional Materials

Theresia Knobloch (TU Wien)

Two-dimensional (2D) materials possess various intriguing properties, making them promising building blocks for future nanoelectronics. For example, 2D semiconductors offer sizable mobilities and high on-currents in thin layers, allowing for excellent gate control in scaled transistors. Nonetheless, to bridge the gap between current device prototypes and commercial applications, multiple challenges must be overcome, including identifying gate stacks that are both scalable and allow for reliable operation throughout the device’s lifetime.

Theresia Knobloch is a postdoctoral researcher focusing on the fabrication, experimental characterization, design, and modeling of nanoelectronic devices based on 2D materials. She obtained her doctoral degree from TU Wien in 2021 and received her doctoral degree in a sub auspiciis doctoral graduation, the highest possible distinction for academic achievements for a doctoral degree in Austria. Theresia performed part of her research as a visiting scholar at MIT, MA, USA, in 2023 and Purdue University, IN, USA, in 2018 and 2019. She received several awards for her work, including the IEEE EDS Ph.D. Student Fellowship in 2021 and the Best Student Paper Award at the DRC in 2020.

TUT 10: SiC Device Reliability and Failure Analysis

Donald Gajewski (Wolfspeed)

In this tutorial, I will give a brief introduction to reliability and failure analysis fundamentals; review key reliability aspects for SiC devices such as bias temperature instability, bipolar stability due to Shockley stacking faults, gate oxide reliability, humidity effects, reverse bias, single event burnout and power cycling; illustrate mission profile analysis techniques; review essential failure analysis techniques such as fault detection, FIB/SEM and EBIC; and review the latest industry consortia standards and guidelines.

Dr. Donald A. Gajewski is the Director of the Reliability Engineering & Failure Analysis Department for Wolfspeed, Inc., covering SiC power MOSFETs, SiC Schottky power diodes, and SiC power modules. He has been in the semiconductor industry reliability profession for 23 years, with previous tenures at Nitronex, Freescale and Motorola. He earned the Ph.D. in physics from the University of California, San Diego. He is the chair of the JEDEC committee JC-70 task group on SiC qualification and reliability standards. He serves on organizing/management committees for the IRPS and ICSCRM conferences.

TUT 11: Interconnect Reliability for Chip Design

Baozhen Li (IBM)

Design Technology Co-optimization (DTCO) has become a critical part for new technology development and applications. For high end and critical application products, reliability co-optimization is an important integral part of DTCO. This tutorial focus on the interconnect reliability optimization considerations for chip design. Discussions will be made from understanding the intention and limitation of various design guidelines & reliability limits to identifying critical areas and robust layouts for different interconnect reliability mechanisms for chip design.

Baozhen Li is a Senior Technical Staff Member in IBM Infrastructure, focusing on reliability and product/technology interactions, working between foundry and chip design and product integration. He has been working on BEOL reliability for more than a quarter of century, serving on technical committees, giving tutorials and invited talks for international reliability and PFA conferences. Baozhen Li holds a Ph.D. degree in Materials Science and Engineering from the University of Notre Dame, USA.

TUT 12: Identifying Material Features & Operation Conditions Targeting Device Neuromorphic Applications

Gennadi Bersuker (M2D Solutions)

A new computational paradigm integrating computing and information storage functionalities requires employing devices with special features. We consider memory formation processes in a promising family of such devices – resistive NVM memristors – employed in various neuromorphic computing implementations. The effectiveness of neuromorphic systems, which are required to achieve several orders of magnitude in energy savings, is defined by the properties of employed NVMs while application conditions may introduce additional constraints (energy consumption, speed, environmental stability, etc.) in order to imitate adaptive synaptic changes. The question of practical importance is whether considered devices can meet use conditions and circuitry operation requirements. In this respect, we assess this technology via novel multi-scale concept that directly links materials to their electrical properties, and the latter to NN algorithms. Projection of this analysis onto brain operations provides insight into possible internal drivers affecting people’s preferences in social and personal choices.

Dr. Gennadi Bersuker focuses on the physical and electrical characterization of microelectronic devices employed in various high-performance applications. Prior to his current position as Principal Scientist & Executive Director in M2D Solutions, he had been working at The Aerospace Corporation FFRDC and semiconductor industry research consortium SEMATECH on advanced technology development and characterization, in particular, neuromorphic computing, scaled transistors, non-volatile and charge trapping memories, III-V and 2D logic, high resolution metrology for multi-material structures among other programs, with the goal to identify materials atomic/structural features affecting device electrical parameters. He is the Editor of IEEE Transactions on Device Materials and Reliability and has been involved in organizing, chairing, or serving as a committee member in numerous technical conferences, including IRPS, IEDM, APS, IRW, etc. He has published over 450 papers on the semiconductor processing, reliability and electronic properties of materials.

TUT 13: Hot-carrier Degradation in Logic Transistors

Michiel Vandemaele (imec)

Hot-carrier degradation (HCD) is a major reliability concern in current and upcoming CMOS technology nodes. In this tutorial, we describe the properties and physical understanding of this FET aging mechanism. We then briefly review past HCD models and explain in depth the modeling of HCD for current technologies. We also address the related problem of self-heating and its interaction with HCD. Additionally, we review different strategies which are used to counteract HCD.

Michiel Vandemaele received the M.Sc. degree in Nanotechnology (KU Leuven and Chalmers University of Technology), the M.Sc. degree in Physics (KU Leuven), and the Ph.D. degree in Electrical Engineering (KU Leuven) in 2015, 2017 and 2023, respectively. His Ph.D. research was conducted in collaboration with imec and focused on the modeling of hot-carrier degradation in future semiconductor technologies like nanowire FETs, nanosheet FETs and forksheet FETs. Michiel Vandemaele is currently a researcher in the Device Reliability and Electrical characterization group at imec, working on incorporating FET aging mechanisms like hot-carrier degradation and bias temperature instability in transistor compact models.

TUT 14-1: GaN RFOLT for 5G/6G Applications

Elias Reese (Qorvo)

GaN utilization in RF communications systems is expanding. Reliability assessment of GaN largely follows proven techniques of static stress conditions to quantify acceleration mechanisms predicting long term degradation, along with short term transient stress conditions. These test methods do not assess multiple stress conditions’ impact and interaction during operation of complex RF/microwave/mmWave circuits. This tutorial presents fundamental RFOLT methods, discusses the complex stress conditions introduced and the value of RFOLT assessing device and circuit reliability.

Elias Reese is Sr. Director of Technology in Qorvo’s High Performance Analog business group. Mr. Reese has worked on advanced microwave circuit and device development for over 40 years, focused on III-V semiconductor and MMIC technology. Following 5 years with Hewlett Packard, Mr. Reese joined Texas Instruments' Microwave Laboratory where he served in multiple technical staff and engineering management roles as that organization transitioned to TriQuint and ultimately Qorvo. Mr. Reese received an M.S.E.E degree from Stanford University and B.S.E.E from The University of Texas at Austin.

TUT 14-2: From Fabrication to Field: The Importance of Semiconductor Reliability Testing in the Age of Wireless Transformation

Roland Shaw (Accel-RF Corporation)

5/6G implementation will enhance mobile broadband service in more ways than the user can imagine. 5/6G will create a unified wireless network operating on a global scale, enabling uses far beyond just consumer-oriented devices. Manufacturers must validate reliability to standards of emerging industry as well as standards already in traditional markets. How can the technical team arm sales and marketing with data to convince customers that un-fielded products will work reliably in the intended environment?

Mr. Roland Shaw is President of Accel-RF Corporation and has over 40 years’ experience in RF/microwave test system development. He is an acknowledged industry leader in developing compound-semiconductor accelerated life test methodologies and co-authored the “Gallium-Arsenide (GaAs) MMIC Reliability Assurance Guideline for Space Applications”, released by NASA-JPL in 1996 as the “guidebook” for space qualification of Gallium-Arsenide MMICs.

Mr. Shaw previously held management and technical positions at Lockheed Martin, Texas Instruments, and was Program Manager on several key projects for NASA-JSC. He has an MSEE from Southern Methodist University (SMU) and BSEE from Texas A&M University.

TUT 15: Plasma Induced Damage (PID): From Basics to Complex Well Charging

Andreas Martin (Infineon Technologies AG)

PID is discussed from the fundamentals to the complex “well charging”. A full description of the PID failure mechanism sets a common understanding for the need of a comprehensive qualification procedure including antenna ratio definition, test structures, stress methods, key analysis parameters for silicon-bulk and SOI technologies. Well charging is under discussion to define antenna design rules for a reliable productive design rule checker. Two competing methods are described from literature with brand-new findings. 

Andreas Martin received his master´s degree in electronic engineering from the Technical University of Darmstadt, Germany. He worked in Tyndall Research Institute in Cork, Republic of Ireland for several years with a focus on MOS gate oxide reliability, before he started 1998 in the corporate reliability department with Infineon Technologies AG in Munich, Germany. Since then he develops methodologies for plasma processing induced charging damage (PID) reliability qualification and fast wafer level reliability (fWLR) monitoring for all technology nodes in-house and for foundry business. He has published several papers on PID characterization methodologies in recent years. He has contributed continuously to technical committees and abstract reviews of various reliability conferences: IIRW, IRPS, ESREF. Mr. Martin is co-chair of the JEDEC 14.2 committee and currently moderates a task group TG142_3 for the development of a standard on a reliability stress method for PID qualification and another task group TG142_2 on the definition of a guideline on fWLR Monitoring.

TUT 16: Electrical Chip-Package-Board Reliability of 2.5D/3D HI Packaged Systems

Mohammad Alam (Purdue University)

To meet the growing demand for integrated circuits (ICs) in increasingly complex and demanding applications, the semiconductor industry has evolved dramatically during the past few decades. Military, space, and avionic electronics must survive harsh environmental conditions, requiring highly reliable specialized packaging like 2.5D/ 3D hetero integration (HI) for greater functionality, device density, and speed. Thus, cross-coupled chip-package-board interactions (CPBIs) result from the proximity of a wide variety of active and passive components and material stacks and processes. This tutorial will provide insights into the emerging electrical reliability challenges typical of a 2.5D/3D packaged IC and offer potential solution schemes to ensure reliable IC operation under the most stringent conditions.

Mohammad Alam is the Jai N. Gupta Distinguished Professor at Purdue University, where his research focuses on the physics and technology of semiconductor devices. From 1995 to 2003, he was with Bell Laboratories, Murray Hill, NJ, working on transistor reliability issues, such as NBTI and TDDB. Since joining Purdue in 2004, Dr. Alam’s research has broadened to include the reliability of self-heated logic and power transistors as well as chip-package interaction in harsh/extreme environments. He is a fellow of IEEE, APS, and AAAS. His awards include the 2006 IEEE Kiyo Tomiyasu Field Medal for contributions to device technology, the 2015 SRC Technical Excellence Award for fundamental contributions to reliability physics, and the 2018 IEEE EDS Award for educating, inspiring, and mentoring electron device professionals around the world. More than 500,000 students worldwide have learned some aspects of semiconductor devices from his web-enabled courses.

TUT 17: Effect of OFF-State Stress on CMOS Devices

Xavier Federspiel (STMicroelectronics)

We review the drift of MOS devices parameters and the MOS device gate dielectric breakdown in off-state mode. Non-conducting hot carrier may induce significant drift of digital and I.O. devices in overdrive conditions, High voltage asymmetrical devices, power switches as well as RF devices.

Gate dielectric breakdown is critical not only as a parasitic phenomenon occurring while performing accelerated non-conducting HCI stress but also can be a limiting factor for High Voltage asymmetrical MOS devices.

Xavier Federspiel received Ph.D in 2001 and has more than 20 years’ experience in Semiconductors reliability. He worked successively with Philips semiconductors, Qimonda GmbH, Dolphin Integration and STMicroelectronics.  He is now CMOS and Imager Reliability Manager in STMicroelectronics R&D Center in Crolles (France).

TUT 18: New Industrial Radiation Paradigms for LEO Satellite Constellations, Full Autonomous Car Driving and Sovereign 3D Chiplets

Philippe Roche (STMicroelectronics)

The growing complexity of today’s automotive vehicles goes side by side with increasingly stringent and multifaceted safety requirements. Just like electromechanical systems in a car, semiconductor components now need to demonstrate high levels of reliability against a variety of failure modes, out of which radiation effects could arguably be among the most unpredictable at system level. While cosmic-ray induced errors may be rare at sea level, the sheer number of land vehicles in a manufacturer’s….

Dr. Philippe Roche is a Company Fellow and Senior Technical Director at STMicroelectronics, Crolles, France. He received the M.S. in 1995, and the Ph.D. grade in semiconductor physics back in 1999. His primary activities are Single Event Effects and Total Ionizing Dose, as well as Ultra Low Voltage IPs, from sub-0.25µm technologies down to FinFET 30 Angstroms. He has been serving in conferences since 1997 as session chair and short course instructor. Philippe has coauthored +300 papers and filed +75 patents and 3 trade marks in radiation hardening. He was appointed Regional Fellow in 2013, then elected by the ST Board as Corporate Fellow in 2020. After 5 years in a product organization designing ASICs, with emphasis on LEO and GEO applications, Philippe is now back to ST Central R&D (FTM/TDP), in charge of new R&D explorations (3D chiplets, GaN, nuclear, 3nm HiRel, etc) with a team of senior experts. Concurrently, Philippe has been also appointed Head of ST R&D Labs & Ecosystems, with CEA-LETI, CNRS, CIME-P (French Silicon broker) as key partners.

TUT 19: Silicon Health & Lifecycle Management, for Data Center and Automotive

Jyotika Athavale, Yervant Zorian (Synopsys)

Recent advances in automotive SOCs, AI accelerators, and HPC engines in data centers have led to an explosion in the adoption of emerging technology nodes and 3DIC/chiplet packages. We will discuss the resiliency challenges for these emerging SOCs, and optimizing the SOC health using prognostics, test and analytic solutions, utilized for managing silicon lifecycle (SLM) for improving quality and yield; and also address aging and degradation challenges for improved RAS and functional safety.

Jyotika Athavale is Director, Silicon Lifecycle Management & RAS architecture at Synopsys. Prior to Synopsys, she was Lead Technologist, Functional Safety Architecture at NVIDIA. Prior to NVIDIA, Jyotika was Principal Engineer (Director) at Intel Corporation leading corporate-wide RAS and Functional Safety architectures.

Jyotika also serves as the 2024 President and Distinguished Visitor of the worldwide IEEE Computer Society, overseeing overall IEEE-CS programs and operations.

She leads and influences several international standardization initiatives. Jyotika chairs the IEEE P2851 family of standards on Functional Safety interoperability which has WG membership from over 30 companies. For her leadership in international safety standardization for IEEE P2851, Jyotika was awarded the 2023 IEEE SA Standards Medallion. And for her leadership in service, she was awarded the IEEE Computer Society Golden Core Award in 2022.

She was recognized as a Distinguished Alumna by her alma-mater VJTI. Jyotika has authored patents and many technical publications in various international conferences and journals. She has pioneered & chaired international workshops and conferences in the field of dependable technologies.

Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founding chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and the 50th International Test Conference (ITC). He founded several other IEEE symposia and workshops.

Dr. Zorian holds 45 US patents, has authored five books, published over 400 refereed papers and received numerous best paper awards. A Fellow of the IEEE
since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, the IEEE Lifetime Contribution Medal of TTTC, and in 2014, the Republic of Armenia's National Medal of Science.

He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

TUT 20: Reliability Challenges of 3D NAND Flash Memory in Harsh Environments

Biswajit Ray (Colorado State University)

3D NAND flash memory is pivotal for large-scale data storage and finds application in aerospace and defense. However, the harsh environmental conditions pose several reliability challenges for 3D NAND, including radiation-induced data corruption and cross-temperature reliability issues. In this tutorial, I will introduce a framework to understand radiation effects on flash memory and present three techniques—electrostatic shielding, defect engineering, and watermark storage—to mitigate radiation effects on commercial 3D NAND.

Biswajit Ray is an Associate Professor of Electrical and Computer Engineering at Colorado State University, where he leads the Reliable and Assured Microelectronics Laboratory. Dr. Ray earned his Ph.D. from Purdue University in West Lafayette, IN, and subsequently worked at SanDisk Corporation in Milpitas, California, contributing to the development of 3D NAND Flash memory technology.

Dr. Ray's research interests encompass electronic devices and systems, with a specific focus on enhancing the security, reliability, non-volatility, and energy efficiency of solid-state storage systems. He holds 20 U.S. issued patents and has authored over 80 research papers published in international journals and conferences. Dr. Ray is the recipient of the NSF EPSCoR Research Fellowship (2020), NSF CAREER Award (2022), and the Best Poster Award at IEEE PAINE (2022).