TBD

Tut1: Introduction to Reliability Physics and Engineering

J.W. McPherson (McPherson Reliability Consulting, LLC)

All materials and devices tend to degrade with time. For this reason, reliability physics is of great theoretical and practical importance. Reliability investigations generally start with measuring the degradation rate for a material/device under stress and then a modeling of the time-to-failure versus the applied stress. The term stress, as used here, is very general: stress will refer to any external agent (electrical, mechanical, chemical, thermal, electrochemical, etc.) that is capable of producing material/device degradation. Time-to-failure occurs when the amount of degradation reaches some critical threshold level. Since devices often require different levels of degradation to induce failure, time-to-failure becomes statistical in nature and two common failure distributions are discussed: Weibull and Lognormal. Time-to-failure (TF) modeling generally assumes either a power law or exponential stress-dependence with either an Arrhenius or Eyring-like activation energy. From these TF models, acceleration factors can be deduced and these tend to serve as the foundation for accelerated testing. During this presentation, several semiconductor failure mechanisms will be reviewed: Electro-Migration (EM), Stress Migration (SM), Time-Dependent Dielectric Breakdown (TDDB), Hot-Carrier Injection (HCI), Negative-Biased Temperature Instability (NBTI), Plasma-Induced Damage (PID), Single-Event Upsets (SEU), Surface Inversion, Thermal Cycling Fatigue, and Corrosion. This tutorial should provide the attendee with a solid foundation for a better understanding of the papers presented at the IRPS.

Dr. J.W. McPherson holds a PhD degree in Physics from Florida State University.  Joe is an IEEE Fellow, a former Texas Instruments Senior Fellow, past General Chairman of the IEEE IRPS, published over 200 papers on reliability physics, authored the reliability chapters for 4 Books, and awarded 20 patents.  Joe is the Founder/CEO of McPherson Reliability Consulting, LLC.  His semiconductor reliability expertise includes device-physics, design-in reliability, wafer-level reliability testing, and assembly-related reliability issues. Several of the reliability models that are used today in the semiconductor industry are closely associated with his name. Most recently Dr. McPherson authored a reliability textbook that is widely used by students and practicing engineers: Reliability Physics and Engineering, Springer Publishing 2010, 2nd Ed. 2013, 3rd Ed. 2019.

Tut2: Machine Learning for Integrated Circuit and Semiconductor Device Reliability Analysis

Elyse Rosenbaum (University of Illinois Urbana-Champaign)

This tutorial is intended for the reliability physics specialist who is curious to learn how machine learning (“ML”) may be applied within her discipline. It will use an expansive definition of machine learning, equating ML to data-driven modeling and contrasting that to models and predictions that are built upon physical knowledge, i.e., mechanistic models. The neural network is a popular model structure for data-driven modeling due to its flexibility; it is often referred to as a universal approximator. This tutorial will cover the basics of neural network training. A survey of works that apply ML to various aspects of reliability analysis will be presented.

Tut3: BEOL and MOL reliability

Shinji Yokogawa (The University of Electro-Communications)

BEOL reliability has played an essential role in semiconductor technologies, from development to quality assurance. Typical wear-out mechanisms include Electromigration (EM), Stress migration/stress-induced voiding (SM/SIV), Thermo-mechanical stability, Low dielectric breakdown (TDDB), and Chip/package interaction CPI). Recently, reliability issues around gate/contacts, or MOL reliability, have been added to the list. Interconnect, via, and contact reliability challenges caused by defects in and at the metal and dielectrics interface, and their generation, are recognized as important issues, even as generations, structures, and materials change. Understanding them and how to suppress them are the key to achieving high reliability. It is also essential to understand the behavior of the lifetime distribution of each integrated circuit to determine the reliability of integrated circuits, which are made up of many segments. This tutorial will present the physical and statistical fundamentals of these mechanisms. Challenges to BEOL/MOL reliability through new technology miniaturization, material sets, and integration schemes will also be discussed.

Shinji Yokogawa is currently a Professor and Director of The Info-Powered Energy System Research Center (i-PERC) at The University of Electro-Communications, Tokyo, Japan. He received a B.S.(1992), M.S.(1994), and Ph.D.(2008) in engineering from The University of Electro- Communications. In 1994, he joined NEC Corp. (later to become NEC Electronics Corp. and Renesas Electronics Corp.), Japan as an engineer and has since been working in the area of reliability. He focused on electromigration, stress-induced voiding, low-k ILD TDDB, and MOL CA-to-PC TDDB issues for technology developments of 130, 90, 65, 55, 45, 40, 32, and 28 nm. From 2008 until 2013, he managed the reliability development team at NEC Electronics Corp., mainly focusing on developing standard CMOS processes and embedded DRAM technology. From 2013 to 2016, he worked at Polytechnic University, administered by the ministry of health, labour, and welfare, Kodaira, Japan. Since April 2016, he has been working at The University of Electro-Communications. He is working for advanced power grid technologies focusing on the available use of renewable energies. His research interests include device reliability (Lithium-ion battery, power device, etc.), reliability statistics, reliability theory, system resilience, and risk management. He has (co)authored over 100 technical papers and serves as a technical committee member and reviewer for leading conferences and journals.

Tut4: LDMOS Reliability: Mechanisms, Methods and Challenges

Guido Sasse (NXP)

LDMOS (lateral double-diffused MOS) transistors are essential components in many mixed-signal and RF applications and are used for their high voltage and power handling capabilities. LDMOS transistors are designed such that they exhibit a large breakdown voltage between drain and source while keeping a low on resistance. To achieve this, LDMOS transistors are designed as asymmetric devices with a lightly-doped region near the drain. Typical operating voltages for LDMOS transistors range from 5V and below up to several 100 V. While there are many similarities with baseline CMOS devices in terms of device reliability, the different architecture and different operating conditions, make that LDMOS transistors have various specific reliability concerns. In this tutorial, we will discuss the basic fundamentals of the LDMOS transistor architecture as well as the relevant wear-out mechanisms affecting device reliability. We will also discuss the similarities and differences with baseline CMOS reliability characterization. Furthermore, in this tutorial the methods, and challenges, to assess the lifetime of LDMOS transistors will be discussed.

Guido T. Sasse is a senior principal reliability engineer at NXP Semiconductors. He obtained his M.Sc. and Ph.D. degrees in electrical engineering from the University of Twente, Enschede, The Netherlands in 2003 and 2008 respectively. His Ph.D. research was on the topic of RF CMOS reliability. After obtaining his Ph.D. he joined NXP in Nijmegen, the Netherlands. Since then, has been active in the field of reliability engineering. He works on device reliability characterization and modelling, process qualification, as well as methods to take into account transistor degradation in circuit design. His focus is on the understanding of transistor degradation mechanisms and the methods to assess their impact on circuit performance. He has been involved in a broad range of silicon-based technologies and devices, ranging from CMOS and FINFET devices to bipolars in BiCMOS and LDMOS in power technologies. 

Guido has (co-)authored various papers on reliability and he has been a reviewer for several journals and conferences. He was on the IEDM technical program committee in 2015 and 2016. Since 2017, he is a member of the IRPS technical program committee, where he was the chair of the process integration subcommittee for IRPS 2022. Currently, he is NXP’s primary member for the JEDEC 14.2 committee (wafer-level reliability). Within this committee he is the chair of the task group to improve the foundry process qualification guidelines (JEP001).

Tut5: FEOL reliability in advanced CMOS nodes

Jen-Hao Lee and Jean P. J. Liao (TSMC)

Continuous CMOS scaling has been accelerating semiconductor evolution for past years, which makes reliability become one of the most critical segments to enable the technology advancement. Today, advanced Logic technologies are the key drivers for Mobile and HPC segments which empowers innovations to enrich our life. However, new physical reliability studies were eagerly required for deeply scaled transistor development. Therefore, this tutorial will elaborate key FEOL reliability mechanisms including time-dependent dielectric breakdown (TDDB), bias temperature stability (BTI), self-heat effect (SHE) and the reliability risk in cascode configuration design. Furthermore, we will address indispensable plasma induced damage (PID) during process period, as well as the risk to degrade transistor performance and gate dielectrics. Time dependent junction degradation (TDJD) is also covered in this tutorial. Moving toward to leading edge technologies, the past conventional methodologies with Logic based bias and failure criterion fall short of enlarging technology envelope on top of meeting field expectation. Also, there has been a circuit application-based qualification approach to offer an accurate assessment on reliability lifetime for all standard and customized usage. The physical based reliability modeling is going to give clear guidance to reserve guard band through IP/chip or system design. Finally, a comprehensive platform with the coverage of “Design for Reliability” has been deployed for different applications which will be a general practice for future technologies.

Jen-Hao Lee received the B.S. and Ph.D. degrees in material science and engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2001 and 2006, respectively. He joined the Taiwan Semiconductor Manufacturing Company Limited (TSMC) since 2007 for fundamental reliability physics, including device reliability, gate oxide integrity as well as product reliability. Currently, he is taking the lead of technology qualification for TSMC's advanced process technologies.

Tut6: Impedance Spectroscopy of MOS systems

Paul K. Hurley (Tyndall National Institute University College Cork)

Impedance spectroscopy of metal-oxide-semiconductor (MOS) systems has been used since the 1960’s, as one of the principal experimental methods to characterize and quantify the properties of the MOS system which is at the heart of logic and memory structures.  The tutorial will cover the following aspects:

• The fundamental measurement of impedance (Z) and phase angle (φ), and how this data is transformed into capacitance (C) and conductance (G) by imposing an equivalent circuit topology on the device under test.

• The significance and applications of using a series and/or a parallel circuit topology.

• The universal relationship between C and G through the Kramers-Kronig equation, and its applications.

• The emergence of MOS systems not dominated by interface defects, with examples of III-V MOS and MOS systems formed on 2 D semiconductors.

• The use of non-local phonon-assisted tunneling to traps to characterize the oxide defect density as a function of space and energy in the InGaAs MOS system.

• A general method to discriminate between interface and oxide defects in MOS structures.

• Impedance spectroscopy of metal-oxide-semiconductor (MOS) at cryogenic temperatures. Do defects still respond?

Paul K. Hurley is a Senior Research Scientist at the Tyndall National Institute (www.tyndall.ie), and a Research Professor in the Department of Chemistry at University College Cork (www.ucc.ie).  Paul leads a research team exploring alternative semiconductor materials and device structures aimed at improving the energy efficiency in the next generation of logic devices. In particular, the group are working on III-V and 2D (e.g., MoS2, WSe2) semiconductors, and exploring how the traditionally passive back end of line in integrated circuits can be turned into an active part of the chip, including logic functions and multilevel non-volatile memory elements. The group are also researching the use of metal-oxide-semiconductor (MOS) systems for the creation of solar fuels through water splitting reactions.  Paul is also a principal investigator in the AMBER centre (https://ambercentre.ie/).  He may be reached at: paul.hurley@tyndall.ie. ORCID ID: https://orcid.org/0000-0001-5137-721X

Tut7: Various reliability issues in DRAM cell transistors

Junsoo Kim (Samsung Electronics)

As the DRAM cell transistor has been increasingly scaled, various reliability concerns have emerged. The read, write, and retention of data are the three main functions of the DRAM cell transistor. Each operation mode has its own issues. Usually, memory chips are pre-screened and repaired before and after packaging. Nevertheless, some reliability measures such as VRT (variable retention time) or Row hammer (an issue of interaction electrically between memory cells by leaking their charges) are difficult to screen, because it is not triggered by thermal or electric field. And suppressing of single event effect contributed by thermal neutrons from cosmic-ray is also necessary to assure the reliability of DRAM chips. In this tutorial, a comprehensive understanding of classic items and recent challenges including soft errors induced cosmic-ray at ground level is presented.

Dr. Junsoo Kim is a Project Lead for DRAM reliability concerns at Samsung R&D Center. He received Ph. D. degrees in Electronic Engineering from the Seoul National University, Seoul, Korea, in 2009. His Ph. D. research focused on the modeling and parameter extraction of electron transport in MOSFETs. In 2009, he joined Samsung electronics, Hwasung, as a process architecture for DRAM devices. Since 2011, he has been responsible for several DRAM cell device integration projects. His current research activities encompass analysis of the characteristics and reliability of transistors.

Tut8: RRAM based AI and reliability

J. Joshua Yang (University of Southern California)

In the era of ‘big data’ and ‘Internet of Things’, the traditional computing architecture based on CMOS hardware has become increasingly inefficient to support Artificial Intelligence (AI) and Machine Learning (ML), which necessitates some emerging technologies, such as RRAM technology (also called memristors when dynamical properties are emphasized). RRAM technology was initially developed for the next-generation nonvolatile memories, for which there are still some remaining challenges to be overcome before a large-scale commercialization is feasible. On the other hand, computing applications are less constrained by such challenges and represent low-hanging fruits for its applications. I will first introduce the state of the art of these devices and how they are used for AI and ML. I will then focus on the challenges and possible solutions for those devices when they are used for AI, with the reliability issue being highlighted.

J. Joshua Yang is a professor of the Department of Electrical and Computer Engineering at the University of Southern California. He was a professor of the ECE department at the University of Massachusetts Amherst between 2015 and 2020. He spent about 8 years at HP Labs between 2007 and 2015, leading the emerging devices team for memory and computing. His current research interest is Post-CMOS hardware for neuromorphic computing, machine learning and artificial intelligence, where he published several pioneering papers and holds 120 granted and about 60 pending US Patents. He is the Founding Chair of the IEEE Neuromorphic Computing Technical Committee, a recipient of the Powell Faculty Research Award and a recipient of UMass distinguished faculty lecturer and UMass Chancellor's Medal, the highest honor of UMass. He serves on the Advisory Boards of a number of prime international journals and conferences, including serving as an associate editor of Science Advances. Dr. Yang is a Clarivate™ Highly Cited Researcher in the field of Cross-Field and the Top Best Scientists in the Research.com list in the Electronics and Electrical Engineering category for 2022. He was elected to the IEEE Fellow and the National Academy of Inventors (NAI) Fellow for his contributions to resistive switching materials and devices for nonvolatile memory and neuromorphic computing.

Tut9: BTI in advanced HKMG for future CMOS Tech nodes

Jacopo Franco (imec)

Negative Bias Temperature Instability (NBTI) has been a primary reliability concern since the early days of Si MOS technology. Decades later, the introduction of high-k dielectrics expanded the concern also towards n-channel devices, with Positive BTI becoming a comparable concern. We will review the basics of BTI, in terms of phenomenology, characterization techniques and proposed models. Next, we will focus on specific BTI challenges in upcoming CMOS technology nodes. In particular, the introduction of nanosheet device architectures with tight vertical pitches, and of stacked device concepts such as the Complementary FET (CFET) are expected to complicate the deployment of common BTI optimization strategies based on sacrificial gate caps and high temperature anneals. Furthermore, the continuously increasing complexity of multi-Vth device offering, comprising a wider range of gate work function metal stacks, might expose additional dielectric defect levels whose role might have been neglected so far. We will highlight the importance of identifying the microscopic defect structures responsible for each BTI signature in advanced gate stacks, in order to successfully develop novel targeted BTI treatments within ever more stringent fabrication constraints. 

Jacopo Franco is a Principal Member of Technical Staff in the Reliability group of the Advanced Reliability, Robustness and Test department of imec, Belgium. He received the B.Sc. (2005) and M.Sc. (2008) from the University of Calabria - Italy, and the Ph.D. degree from KU Leuven - Belgium (2013) in Electrical Engineering. His research focuses on CMOS FEOL reliability characterization, optimization, and modelling, and in particular: i) on gate stack development for novel device technologies (SiGe, Ge, III-V, IGZO), architectures (finFETs, FD-SOI, Nanowires, Nanosheets), and integration schemes (Sequential 3D tier stacking, CFETs); ii) on characterization and physics-based modelling of FEOL degradation mechanisms (BTI, Hot Carrier, Off-state degradation, TDDB, RTN, time-dependent variability); iii) on reliability compact models to accurately propagate individual device aging to circuit level. He has (co-)authored 250+ contributed or invited papers and 3 patent families, and he is a recipient of several IEEE awards: Best Student Paper at SISC (2009), EDS Ph.D. Student Fellowship (2012), Paul Rappaport Award (2011), Best (2012, 2022), Outstanding (2014), and Best Student (2016) paper awards at IRPS. He has been serving in various functions on the Technical Program Committees of IRPS (Chair of the ‘XT-Transistors’ subcommittee in 2020), SISC, IIRW, ESREF, WoDiM and InFOS conferences, and as an Editor of IEEE Transactions on Device and Materials Reliability (2017-2020) and of IEEE Transactions on Electron Devices (2020-2022).

Tut10: Emerging memories reliability: from device to applications

Cristian Zambelli (University of Ferrara)

Emerging memory technologies such as Resistive Switching Memories (RRAM), Phase Change Memory (PCM) and Magnetic RAM (MRAM) are disrupting the storage hierarchy by offering performance metrics at the intersection of DRAMs (used as main working memory in almost all computer architecture) and NAND Flash (the core of bulk storage systems such as Solid-State Drives). A considerable number of embedded and high-performance computing (HPC) systems are envisioning the adoption of these Storage Class Memories (SCM) in their designs to improve latency, throughput, and power consumption figures. In addition, by arranging such revolutionary memory cell concepts in crossbar array topologies, we testify unprecedented integration scenario such as neuromorphic and in-memory computing, thus enabling energy-efficient non-Von Neumann architectures. The path towards the commercialization of emerging memory technologies is however strictly dependent on the reliability features offered both on the short-term (disturbs and read/write stability) and on the long-term (endurance and data retention). In this tutorial, we will address three technologies in the landscape of the emerging memories by showing how their physical working principles and their integration characteristics pose significant reliability threats that must be mitigated either with a careful device engineering or with a system-level approach. A link between the reliability figures of merit and the application scenario foreseen for each technology is explored throughout the entire tutorial.

Cristian Zambelli received the M.Sc. and the Ph.D. degrees in Electronics Engineering and Engineering Science from the University of Ferrara, Ferrara, Italy, in 2008 and 2012, respectively. In 2015, he joined the Department of Engineering with the same institution where currently holds an Associate Professor position. His current research interests include the electrical characterization and reliability modeling at array-level of different non-volatile memory technologies such as Flash (Planar and 3D), Resistive RAM (RRAM), Phase Change Memories (PCM), and Magnetic RAM (MRAM). He is also interested in the development of cross-layer techniques for memory reliability/performance trade-off exploitation in Solid State Drives (SSDs), Neuromorphic computing accelerators and storage in High Performance Computing contexts.

Tut11: Heterogenous Integration Reliability Challenges and Roadmap

Richard Rao (Marvell Technology)

This tutorial examines the reliability implications of ‘SysMoore’, i.e. system-level heterogeneous integration (HI), that is being developed as a means to keep delivering the rate of performance increase, that we have come to expect because of Moore’s Law. Increasing system complexity, functionality, diversity, and density, as a result of the twin drives for HI and on-chip advances, will pose new challenges for meeting and verifying customers’ reliability targets. Multifunctional HI systems of the future are expected be complex multiscale and multiphysics systems. Heterogeneous integration requires a convergence between the semiconductor industry and the packaging industry, and a unified reliability approach across the entire product architecture hierarchy from device level to package, boards/ modules, and systems.  The resulting complex chip-package-board interactions (CPBI) will pose new reliability challenges and will need to be addressed by an integrated reliability team across all these levels of device-to-system integration, to meet the customer’s reliability targets. HI reliability engineers will also need to meet holistic constraints such as reducing the time required for new product introduction (NPI) and minimizing cost of ownership over the life-cycle of successive generations of products.  Such an integrated approach towards reliability will require a rigorous, disciplined, and proactive fusion approach that strategically combines a bottom-up reliability physics approach with a top-down approach that leverages powerful artificial intelligence algorithms and the unprecedented levels of real-time field performance data, service condition data, product stress data and system/component reliability data that is becoming available via IoT infrastructure. This tutorial lays out the scope, challenges, disruptive opportunities, and potential approaches for achieving such an integrated reliability approach for HI technologies, that are likely to emerge over the next 0-5, 5-10 and 10-15 years

This tutorial will focus on the following aspects of heterogenous integration reliability.

1. Introduction of heterogenous integration packages such as chiplet, 2.5D and 3D package integrations.

2. Reliability failure modes and degradation mechanisms for multi-level interconnects in the heterogenous integration system such as TSV, uBumps, RDLs and hybrid bonding, etc.

3. Chip package and board integrations

4. Design for reliability

5. Qualification for reliability

Richard Rao is currently a Senior Principal Engineer at Marvell Technology and a Senior Member of IEEE.  He was a Technical Fellow of Microsemi (Microchip) Corp and a consultant engineer at Ericson Inc. His responsibilities include the development of design for reliability flows for advanced circuits, packaging, and chip to package interaction. He was the chair of IEEE EPS Reliability Technical Committee and co-authoring the reliability roadmap chapter for the Heterogenous Integration Roadmap. He is also the general chair and technical program chair for the IEEE REPP (Reliability of Electronics and Photonics Packaging) Symposium.  He has a Ph.D. degree in solid mechanics of materials from the University of Science and Technology of China. Prior to joining Marvell, Dr. Rao held various academic and technical positions in reliability physics and engineering. He was an associate professor at University of Science and Technology of China, a research fellow at Northwestern University, Evanston, IL, USA and National Science and Technology Board of Singapore. 

Tut12: MEMS reliability

Ashwin A. Seshia (Cambridge University)

Microelectromechanical systems (MEMS) technology has made rapid strides in addressing large volume as well as niche applications such as physical and chemical sensors, timing and frequency control, and component technologies for radio frequency communication systems. Microelectromechanical devices are fabricated using semiconductor batch manufacturing techniques and often consist of electrically interfaced moving parts on a silicon chip, introducing additional criteria for reliability assessment. This tutorial will cover an overview of the physical mechanisms underpinning performance degradation and failure in microelectromechanical systems while maintaining a focus on free standing silicon-based microelectromechanical devices. Physical models underpinning the behaviour of specific types of devices will be introduced including (1) inertial sensors, (2) resonators, and (3) vibration energy harvesters. Aspects relating to performance over temperature/temperature cycling, shock and vibration loading, and other environmental conditions will be covered. A discussion of various approaches to address the development of high yielding, high-performance parts developed at the device, process, assembly and packaging, and system integration levels will be discussed.

Tut13: Reliability Characterization of CMOS Ring Oscillator Circuits in scaled CMOS Technologies

Andreas Kerber (Intel)

Reliability characterization of CMOS technologies is primarily focused on bias temperature instability (BTI), hot carrier injection (HCI) and time dependent dielectric breakdown (TDDB) using discrete devices. In recent years, characterization methods were extended from DC to AC waveforms to better capture the widely discussed recovery effects and to assess lifetime under switching conditions mimicking digital operation.

In this tutorial we focus on reliability characterization of CMOS ring-oscillators (RO) circuits representing a fundamental digital circuit block. We discuss time resolved RO frequency measurements and its importance in capturing the BTI component in digital circuit aging. We identify HCI contributions in RO by varying test temperature and using different test structure designs. We also address the relevance of self-heating and attempt to correlate the aging in discrete devices to degradation in ROs in scaled CMOS technologies.

Andreas Kerber received his Diploma in physics from the University of Innsbruck, Austria, in 2001, and a PhD in electrical engineering from the TU-Darmstadt, Germany, with honors in 2004. From 1999 to 2000 he was an intern at Bell Laboratories, Lucent Technologies (Murray Hill, NJ, USA) working on the electrical characterization of ultra-thin gate oxides. From 2001 to 2003, he was the Infineon Technologies assignee to International SEMATECH at IMEC in Leuven, Belgium, where he was involved in the electrical characterization of alternative gate dielectrics for sub-100 nm CMOS technologies. From 2004 to 2006, he was with the Reliability Methodology Department at Infineon Technologies in Munich, Germany, responsible for the dielectric reliability qualification of process technology transfers of 110 and 90 nm memory products. During that time, he developed a low-cost, fast wafer-level data acquisition setup for time-dependent dielectric breakdown (TDDB) testing with sub-ms time resolution. From 2006 to 2018 he was working for AMD in Yorktown Heights, NY, and GLOBALFOUNDRIES in Malta and East-Fishkill, NY, as a Principal Member of Technical Staff on front-end-of-line (FEOL) reliability research with focus on metal gate / high-k CMOS process technology, advanced transistor architecture and device-to-circuit reliability correlation. From 2018 to 2019 he was with Skorpios Technologies in Albuquerque, NM, working on reliability of Si-photonic devices. From Nov. 2019 to March 2021, he was with ON-Semiconductor in Santa Clara, CA working on product quality management of CMOS image sensors for automotive, consumer and industrial markets. Since March 2021 he is with Intel in Santa Clara, CA working on CMOS and interconnect reliability for 3D-NAND technology. 

Dr. Kerber has contributed to more than 110 journal and conference publications and presented his work at international conferences, including the IEDM, VLSI and IRPS. In addition, he has presented tutorials on metal gate / high-k reliability characterization at the IIRW, IRPS and ICMTS. Dr. Kerber has served as a technical program committee member for the SISC, IRPS, IIRW, IEDM, Infos, ESSDERC, is a Senior Member of the IEEE and a Distinguished Lecturer (DL) for the IEEE Electron Devices Society.

Tut14: Design for Reliability in Product Development

Ranjani Muthiah (Google)

A systematic, proactive approach to product reliability is essential to deliver highly reliable products. This tutorial will outline the components of a Design for Reliability program that is key for successful Product Development. Methodologies used in product design and manufacturing for reliability in Photonic ICs will be reviewed. Accelerated stress testing strategies and their applicability to field use conditions will be discussed. Details and considerations for reliability in product development, with examples from highly reliable Photonic Integrated Circuits, will be presented.

Ranjani Muthiah is Director of Hardware Engineering at Google. She is responsible for Yield/Test Engineering and Reliability for the Raxium microLED technology. Prior to joining Google in 2022, she was Associate Vice President for Quality & Reliability at Inphi Corp., acquired by Marvell in 2021. Ranjani was responsible for Quality of the broad portfolio of Inphi’s IC and Optical data communication products. Previously, Ranjani was with Infinera as Sr. Manager, Reliability Engineering in the Optical Integrated Components Group. She has been instrumental in successfully productizing large scale Photonic Integrated Circuit based modules, in Indium Phosphide (InP) and Silicon platforms, with excellent reliability.

Ranjani received her Ph.D. in Materials Science & Engineering from the University of Pennsylvania and her B.Tech. in Metallurgical Engineering from the IIT-Varanasi, India. Dr. Muthiah has published over 25 papers in technical journals / conferences and is a co-inventor on multiple patents

Tut15: Reliability Challenges for Si Photonics Products

Arif Zaman & Quan Tran (Intel)

Intel’s Silicon Photonics (SiP) program overview will be provided. Next, reliability challenges and qualification methodology of SiP components are discussed. In particular, the challenges in qualification of those components for integrating them into LiDAR application are addressed. Finally, the methodology to qualify optical transceiver products with integrated SiP components is presented

Arif Zaman is a TD Q&R Engineering Director at Intel Silicon Photonics Division with over 25 years of semiconductor industry experience. Arif has been leading Intel’s Silicon Photonics Quality & Reliability organization, and responsible for components, Fab, Modules, OSATs and Contract Manufacturers.  He has delivered industry leading reliability of Intel’s entire Silicon Photonics portfolio. Prior to join Intel, Arif worked for MACOM, Qualcomm, Qorvo, Skyworks, and other companies. Arif received a Ph.D. degree in Electrical Engineering from Florida Institute of Technology specialized in designing compound semiconductor devices and processes. 

Neil Caranto is a technical lead with Intel’s silicon photonics product reliability group with in depth focus on lasers and SOAs reliability per data communication and automotive market standards. He has more than two decades industrial experience and received his Ph.D. in the field of optical fiber sensors from Victoria University, Australia. He is currently responsible for the reliability of Intel’s LIDAR PICs and its components.

Carsten Brandt received M.S and B.S. degrees in Materials Science and Engineering from New Mexico Tech and has been a Quality and Reliability engineer at Intel since 2001. He leads the Intel Silicon Photonics Fab Process Certification efforts and has been heavily engaged in Intel’s Silicon Photonics component qualifications with focus on Rx devices. 

Quan Tran is an Engineering TD manager at Intel’s Silicon Photonics Product Division with focus on optical transceiver reliability. He has been with Intel for more than 24 years working on various areas including thin-film fracture mechanics for semiconductor processes and electronic packaging applications, characterization and reliability of MEMS (micro-electro mechanical systems) devices for RF front end communication and memory storage applications, reliability of NAND memory, and reliability of hybrid lasers when integrated into optical transceiver products. He authored/co-authored more than 8 papers and 16 patents. He received a B.S. degree in Materials Science and Engineering with a minor in Physics from University of California at Berkeley and an M.S. degree in Materials Science and Engineering from Stanford University.

Tut16: Reliability of encapsulating molding compounds for electronic packaging subjected to high field and different environmental conditions

Susanna Reggiani (University of Bologna)

The study of physical properties of encapsulation materials used in power electronic industry has raised increasing interest in recent years, as package design is a key aspect in device reliability. Polymeric molding compounds are known to be source of surface charging effects, mainly attributed to dielectric losses, ionic conductivity and charge accumulation at the interface with the passivation layers. The understanding of charge spreading is of primary importance to improve device reliability at the design stage. Given the technological importance, a number of novel characterization methods have been recently proposed. Among them, low-field conductivity, dielectric spectroscopy and pulsed electro-acoustic characterizations have been implemented on bulk samples, while special test chips with integrated charge sensors allowed for the characterization of the lateral charge spreading in more realistic operating conditions. Special fucus has been devoted to environments with high humidity conditions showing significant changes in the dielectric properties. Numerical simulations based on commercial TCAD tools were also carried out with the purpose of a deeper physical insight. High-voltage lateral devices like, e.g., LDMOS transistors or GaN HEMTs, are expected to be strongly impacted by mobile charges on the overlying isolation. In this tutorial, an investigation of the package-induced effects will be addressed by reviewing the main features of polymers, their numerical simulation and their characterization at different conditions. 

Susanna Reggiani is Full Professor at the University of Bologna, Italy, with the Department of Electronics (DEI) and the Advanced Research Center for Electronic Systems (ARCES). She received her Ph.D. degree in Electrical Engineering at the University of Bologna in 2001. Her scientific activity has been devoted to the physics-based modeling and characterization of solid-state electronic devices, with special emphasis on transport models in semiconductors. Since 2007 she has been involved in Projects dealing with the TCAD analysis of power MOSFETs, modeling and characterization of hot-carrier stress degradation, modeling of package influences on high-voltage semiconductor FETs, TCAD study of the reliability of GaN-on-Si HEMTs, development of physically based models for SiC-based power devices. She is author/co-author of more than 200 papers published in referred international journals and proceedings of international conferences. 

Tut17: Device and Interconnect Reliability Implications for Digital and Analog Circuit Design

Sachin S. Sapatnekar (University of Minnesota)

Reliability problems are a serious issue in modern digital and analog circuits. As design moves to FinFET/GAAFET nodes and beyond, devices and interconnects undergo increasing levels of stress as they carry higher currents (for digital circuits), or prolonged continuous bias currents (for analog circuits), or are subjected to prolonged voltage stresses. This presentation presents an overview of methods for analyzing and optimizing VLSI circuit reliability, going from device modeling approaches to circuit and system optimization at an appropriate level of abstraction for the circuit/system designer.  As typical industry design flows find detailed physics-based models to be too complex for practical use, and instead use empirical models that provide fewer insights, recent efforts at the circuit level have attempted to close this gap.  For example, for the problem of electromigration (EM) analysis, recent work has reduced the complexity of solving the physics-based equations that model EM, creating credible alternatives to empirical methods.  The focus of this tutorial is on providing the link between physics-based models for bias temperature, hot-carrier injection, time-dependent dielectric breakdown, and electromigration, and their deployment into simulation and optimization techniques at the chip or system level, for both digital and analog systems.

Sachin S. Sapatnekar received the Ph.D. degree from the University of Illinois at Urbana-Champaign in 1992.  He is on the faculty of the University of Minnesota, where he holds the Distinguished McKnight University Professorship and the Henle Chair Professorship in Electrical and Computer Engineering. His research is related to developing CAD techniques for the analysis and optimization of circuit performance, currently focused on analog and digital CMOS circuits. He has served as Editor-in-Chief of the IEEE Transactions on CAD and General Chair for the ACM/IEEE Design Automation Conference (DAC).  He is a recipient of twelve conference Best Paper Awards, the Semiconductor Research Corporation's Technical Excellence Award, and the Semiconductor Industry Association University Research Award. He is a Fellow of the IEEE and the ACM.

Tut18: The role of defects in the dynamic lifetime of GaN power devices

Clemens Ostermaier (Infineon Technologies)

Gallium nitride (GaN) offers fundamental advantages over silicon. In particular the higher critical electrical field makes it very attractive for power semiconductor devices with outstanding specific dynamic on-state resistance and smaller capacitances compared to silicon switches, which makes GaN HEMTs great for high speed switching.

 Besides the polarization charge induced 2-dimensional electron gas, two key defects control the device behavior: Interface defect states controlling the electron concentration in the lateral device channel and deep defect states in the buffer enabling the vertical buffer insulation.

This tutorial aims to review the latest understanding of those device behavior defining defects and look further into their role in lifetime limiting robustness issues of GaN devices under dynamic switching conditions. A particular focus will be effects of hot carriers trapping in the device during hard-switching stress conditions leading a steady increase in dynamic on-resistance and also hard failures.

Clemens Ostermaier has received his master’s degree in semiconductor engineering from Kyungpook National University in South Korea in 2008 and his doctoral degree in electrical engineering from Vienna University of Technology in 2011, where he rejoined in 2019 as university lecturer. Since 2010 he is working at Infineon Technologies Austria on GaN power devices with special interest and passion on the technology, material and device physics, and reliability aspects. In this role he has supervised more than 20 PhD and master students and co-authored over 30 peer-reviewed scientific journal publications, more than 60 conference contributions and over 20 international patent and patent applications in power semiconductors.

Tut19: Radiation Effects in a Post-Moore World

Dan Fleetwood (Vanderbilt University)

In this tutorial a number of milestones in the evolution and understanding of total-ionizing-dose and single-event effects are reviewed within the context of classical Dennard scaling. The discussion will focus on the discovery of fundamental mechanisms, development of radiation-tolerant IC technology, and increasing maturity and complexity of Si-MOS-based devices, circuits, and systems. Examples are shown that illustrate how the end of Dennard scaling has influenced radiation effects in current technology generations, due to the increasingly complex and diverse materials and devices that are now incorporated. The radiation responses of devices with alternative channels to silicon and transistors based on 2-D materials are discussed, with an emphasis on the mechanisms of defect formation. The utility of low-frequency (1/f) noise measurements in defect characterization will be discussed within this context. In the future, many types of microelectronic devices and ICs will become more vulnerable to radiation effects and more difficult to test in a practical and cost-effective manner. This will become an ongoing challenge for the international radiation effects community, particularly for ultimately scaled devices and/or quantum computing.

Dan Fleetwood received his Ph.D. from Purdue University in 1984. He joined Sandia National Laboratories in 1984 as a Member of the Technical Staff. In 1990, he was named a Distinguished Member of the Technical Staff. Dan accepted a position as Professor of Electrical Engineering at Vanderbilt University in 1999, and holds a secondary appointment as Professor of Physics. In 2001-2003 he served as Associate Dean for Research in the School of Engineering. From 2003-2020 he served as Chairman of Vanderbilt’s Electrical Engineering and Computer Science Department. In 2009 he was named Olin H. Landreth Chair in Engineering, a position that he still holds. Dan is author or co-author of more than 600 publications on radiation effects, defects in microelectronic devices, and low frequency noise, which have been cited more than 26,000 times (Google Scholar). He received the 2009 IEEE Nuclear and Plasma Sciences (NPSS) Merit Award, the society’s highest technical honor, and is a Fellow of IEEE, the American Physical Society, and the American Association of the Advancement of Science. Dan currently serves as NPSS Distinguished Lecturers Chair, Senior Editor for Radiation Effects for the IEEE Transactions on Nuclear Science, and Vice-Chair, Publications, for the Radiation Effects Technical Committee of the NPSS.

Tut20: Reliability and Variability of CMOS Devices at Cryogenic Temperatures

Alexander Grill (imec)

Integrating CMOS circuits and qubits at cryogenic temperatures is one of the key challenges to mitigate wiring constraints and ensure signal integrity to enable up-scaling of quantum computers. While operating in the GHz-regime, interfaces between classical and quantum circuits need to maintain ultra-low power consumption together with very low noise figures. One approach to reduce power consumption is to optimize designs towards operation at lower supply voltages. However, this also reduces the tolerable margins on variability, parameter drift, and device to device variations. In this tutorial, I will present an overview on the physics of cryo-CMOS devices with a special focus on device variability and reliability. I will present our current understanding of low-frequency noise and modelling of charge trapping kinetics at cryogenic temperatures. I will also highlight the importance of integrated metrology structures to overcome the measurement bottleneck arising in most common cryogenic probers.

Alexander Grill studied Microelectronics at the Vienna University of Technology, where he received his master’s degree in 2013 and his doctoral degree in 2018. He is currently working as a researcher for cryogenic electronics at imec, Leuven. His main scientific interests are characterization and modeling of semiconductor devices at cryogenic temperatures with a special focus on charge trapping and reliability. His current focus is time-zero variability and the extraction of physical defect properties at cryogenic temperatures to enable technology optimization for low-noise, low-power circuits at cryogenic temperatures.

Tut21: Physical Modeling of Reliability Challenges in SiC Power Devices

Michael Waltl (TU Vienna)

State-of-the-art SiC power MOSFETs mostly use a vertical device architecture which has the advantage of having a high blocking voltage and comparable small on-resistance, maintaining a small chip area compared to lateral device structures. Besides these major advantages, vertical SiC MOSFETs exhibit higher carrier mobility due to reduced trap density in the vicinity of the conduction band edge, but larger defect densities within the SiC bandgap. To passivate as many of these defects as possible various post-oxidation anneals have been studied in the past. But still, a considerable number of traps remain, which are the central origin for dynamic changes e.g. in the threshold voltage, which becomes visible as hysteresis of voltage sweep measurement and experiments performed to investigate bias temperature instabilities. It has to be noted that the physical understanding and modeling of the defects and their impact on the devices is vital to enable studying device performance degradation and its impact on the behavior of circuits. In this talk, an overview of reliability challenges and recent advances in SiC power MOSFETs is given. Also, the latest modeling efforts toward a consistent explanation of device electrostatics, e.g. the simulation of IV sweeps, but also the explanation of transient effects by means of TCAD simulations, are addressed. Finally, based on the calibrated simulations, the model parameters can be linked to certain trap candidates. However, for the SiC material system, there is a large variety of potential trap candidates available that might contribute to charge trapping.

Michael Waltl is an Assistant professor at TU Wien in Vienna, Austria. He received his Master’s degree (Dipl.-Ing.) and his doctoral degree (Dr.techn.) in Microelectronics from TU Wien in 2011 and 2016, respectively. He is the co-author or author of over 150 articles in journals and conference proceedings. Furthermore, Dr. Waltl is the director of the Christian Doppler Laboratory for single defect spectroscopy in semiconductor devices and leads the device characterization laboratory at the IuE at the TUW. He is the (co-)recipient of various best paper awards (IIRW2014, DRC2019, IIRW2019, IEDM2019, etc.) and serves on the technical program and management committee of international conferences and workshops (IEDM, IRPS, IIRW, etc.). Based on his expertise, Dr. Waltl is regularly invited as a reviewer of numerous renowned Journals, including IEEE TED, Microelectronics Reliability, Journal of Applied Physics, and many more.

Tut22: Automotive Electronics Reliability – Challenges and Opportunities

Pradeep Lall (Auburn University)

The modern car has increased semiconductor content and dollar value.  Semiconductors enable the majority of innovations in automotive.  The increased emphasis on autonomous driving and the electrification of vehicles has resulted in enormous changes for semiconductors and packaging.  The design, materials, and reliability strategies for automotive electronics will be presented.  Electronics are increasingly being used in automotive platforms for various mission-critical and safety-critical activities, such as guidance, navigation, control, charging, sensing, and operator interaction.  Over the last two decades, automotive platforms have expanded to incorporate hybrid and fully-electric vehicles.  Much of the electronics is located under the car’s hood or in the trunk, where temperatures and vibration levels are far higher than in consumer office applications.  During the vehicle’s use-life, electronics in the automotive underhood may be exposed to sustained high temperatures of 125-150°C for extended periods of time.  The automotive electronics council (AEC) has graded electronics for automotive purposes into four categories: grade-0, grade-1, grade-2, and grade-3.  Grade-0 components have the most demanding criteria of the four grade categories, with predicted power temperature cycling ranging from -40°C to +150°C for 1000 cycles and ambient temperature cycling ranging from -55°C to +150°C for 2000 cycles.  Furthermore, the grade-0 components are expected to be capable of sustaining high-temperature storage for 1000 hours at 175°C.  With the introduction of new packaging architectures, packaging applications have continued to evolve, allowing for powerful computing on mobile automobile platforms.  New materials and integration technologies have also emerged, allowing for tighter integration of electronics sensing and processing into the structural characteristics of the vehicle.  The automobile platform faces a series of constraints particular to the real-time context for enabling sophisticated functionality. 

Pradeep Lall is the MacFarlane Endowed Distinguished Professor with the Department of Mechanical Engineering and Director of the NSF-CAVE3 Electronics Research Center at Auburn University.  He holds Joint Courtesy Appointments in the Department of Electrical and Computer Engineering and the Department of Finance.  He is a member of the technical council and academic co-lead of automotive TWG and asset monitoring TWG of NextFlex Manufacturing Institute.  He is the author and co-author of 2-books, 14 book chapters, and over 850 journal and conference papers in the field of electronics reliability, manufacturing, safety, test, energy efficiency, and survivability.  Dr. Lall is a fellow of the ASME, a fellow of the IEEE, a Fellow of NextFlex Manufacturing Institute, and a Fellow of the Alabama Academy of Science.  He is a recipient of the IEEE Biedenbach Outstanding Engineering Educator Award, Auburn University Research Advisory Board’s Advancement of Research and Scholarship Achievement Award, IEEE Sustained Outstanding Technical Contributions Award, NSF-IUCRC Association’s Alex Schwarzkopf Award, Alabama Academy of Science Wright A, Gardner Award, IEEE Exceptional Technical Achievement Award, ASME-EPPD Applied Mechanics Award, SMTA’s Member of Technical Distinction Award, Auburn University’s Creative Research and Scholarship Award, SEC Faculty Achievement Award, Samuel Ginn College of Engineering Senior Faculty Research Award, Three-Motorola Outstanding Innovation Awards, Five-Motorola Engineering Awards, and over Forty Best-Paper Awards at national and international conferences.  Dr. Lall is the founding faculty advisor for the SMTA student chapter at Auburn University and a member of the editorial advisory board for SMTA Journal.  

Tut23: Soft Errors – from simple devices to complex systems

Indranil Chatterjee (Airbus)

With diminishing feature sizes, radiation effects in semiconductor devices continue to be the dominant failure mechanism compared to all other "hard" reliability failure modes combined. With the push to deploy data-intensive edge-computing applications, be it in aircraft, satellites, or autonomous vehicles, soft-errors have a strong impact on system reliability, dependability, and availability. These applications use commercially available high-performance components which do not use any Radiation-Hardening-by-Design (RHBD) concepts and Size, Weight, and Power (SWaP) are the key metrics, making them susceptible to radiation induced faults. Thus, system-level handling and mitigation of soft errors is imperative for successful deployment of these components in radiation environments. In this short course, an overview of the single-event effects impacting advanced semiconductor nodes will be discussed. Key metrics for designing SEE tests, such as sample preparation, biasing conditions, thermal impacts, internal fault tolerance mechanisms, etc. will be covered. Being able to determine the interplay of these variables is an integral part of designing a test to meet the needs of a specific application. Efficacies and limitations of board-level SEE testing, as opposed to component-level SEE testing, will also be discussed. Finally, the course will focus on the system level aspects of soft errors, and provide a global overview of how complex systems such as autonomous vehicles, aircraft, or satellites handle soft errors, and, ensure performance and reliability in various application environments, from ground to space.

Indranil Chatterjee (IEEE SM’19, M’14) received his M.S. and Ph.D. degrees in electrical engineering from Vanderbilt University, USA in 2014. From 2014 to 2016, he worked as a Postdoctoral Scientist in GaN power device development and reliability with the University of Bristol, UK. Since 2016, he is with Airbus in Friedrichshafen, Germany where he is presently the Airbus eXpert on Discrete and Integrated Semiconductor Devices involved in R&D, design, radiation and reliability analysis of critical electronic systems for satellites, and interplanetary probes. His research interests include Radiation Tolerance of Semiconductor Devices, Semiconductor Device Physics, Reliability, and Novel Devices. Dr. Chatterjee is a Senior Member of IEEE, and has authored and co-authored more than 50 papers in international journals and conferences. 

Tut24: Reliability of Semiconductor Spin Qubits for Quantum Computing

Michael Jura (HRL Laboratories)

Over the past two decades significant progress has been made using spins in semiconductors as qubits for quantum computing, yet semiconductor qubits currently trail other architectures (including those utilizing superconductors or trapped ions) in number of demonstrated qubits. No architecture has yet achieved the number of qubits needed to reach the promise of quantum computing, and semiconducting qubits’ potential lies in the ability to scale more rapidly, both in terms of quantum-coherent control and fabrication. In this tutorial, we review gate-defined semiconductor spin qubits and discuss yield and reliability concerns that are unique to the technology, as well as those common with CMOS integrated circuits. We consider the demands for spin qubits applied to device and process design and process control. We review the fabrication and operation of major types of spin qubits, including donor spin qubits, single-spin “Loss-DiVincenzo” qubits, and triple-spin exchange-only qubits. We next discuss device yield failure mechanisms at quantum-relevant temperatures (typically ~0.1 K) such as poor gate connectivity, poor signal delivery, electrostatic disorder (similar to threshold uniformity), charge noise, magnetic noise, and accessibility of excited quantum states. Reliability issues include threshold drift, repeated thermal cycling, and electrostatic discharge. Finally, we discuss HRL’s approach to reliable quantum technology: the SLEDGE (single-layer etch-defined gate electrode) platform.

Dr. Michael Jura is a Senior Physicist at HRL Laboratories, where he has worked since 2014. He leads the Materials Characterization group, which tests quantum dot spin qubit devices at low temperature, and he also directs qubit failure analysis and quantum yield engineering efforts. He has helped develop and validate novel spin qubit designs that will enable device scaling and increase fidelity. Prior to joining HRL, Dr. Jura worked at a start-up company using silicon nanowires to improve the efficiency of solar cells. He earned his Ph.D. in Applied Physics from Stanford and bachelor’s degrees in Physics and Electrical Engineering/Computer Science from MIT.

Tut25: Insulators for Devices based on 2D Materials

Tibor Grasser (TU Vienna)

Despite the breathtaking progress already achieved for 2D electronic devices, they are still far from exploiting their predicted performance potential. This is in part due to the lack of scalable insulators, which would go along with 2D materials as nicely as SiO2 goes with silicon. As a result, there is still no commercially competitive 2D transistor technology available today. 

The selection of suitable insulators for 2D nanoelectronics represents an enormous challenge. However, this problem is of key importance, since scaling of 2D semiconductors towards sub-10nm channel lengths is only possible with gate insulators scalable down to sub-1nm equivalent oxide thicknesses (EOT). In order to achieve competitive device performance, these insulators need to meet stringent requirements regarding (i) low gate leakage currents, (ii) low density of interface traps, (iii) low density of border insulator traps and (iv) high dielectric strength. 

The insulators typically used for 2D electronic devices are amorphous 3D oxides known from Si technologies (SiO2, HfO2, Al2O3), while native 2D oxides (MO3, WO3 and Bi2SeO5), layered 2D crystals (hBN, mica) and ionic 3D crystals (CaF2 and other fluorides like SrF2, MgF2) have received increasing attention. 3D oxides form poor quality interfaces with 2D semiconductors and contain border traps which severely perturb stable device operation.  Native oxides, on the other hand, are often non-stoichiometric due to the lack of well-adjusted oxidation methods and thus have a limited dielectric stability and inherently narrow bandgaps. As the most popular candidate, the layered 2D insulator hBN forms excellent van der Waals interfaces with 2D semiconductors, but has mediocre dielectric properties resulting in excessive leakage currents for sub-1nm EOT. The potential of other 2D insulators (e.g. mica) is currently unclear, in part due to the absence of scalable growth techniques.  Finally, very promising insulators for 2D electronics are 3D ionic crystals like CaF2 which form well-defined interfaces to 2D channel materials. In contrast to hBN, fluorides have good dielectric properties and thus exhibit low gate leakage currents. This tutorial will address the current state of the art and summarize the main problems together with potential solutions.

Prof. Tibor Grasser is an IEEE Fellow and head of the Institute for Microelectronics at TU Wien.  He has edited various books, e.g. on the bias temperature instability, hot carrier degradation, and low-frequency noise (all with Springer), is a distinguished lecturer of the IEEE EDS, has been involved in outstanding conferences such as IEDM (General Chair 2021), IRPS, ESSDERC (TPC Co-Chair 2015), IIRW (General Chair 2014), and SISPAD (General Chair 2007), is a recipient of the Best and Outstanding Paper Awards at IRPS (2008, 2010, 2012, and 2014), IPFA (2013 and 2014), ESREF (2008) and the IEEE EDS Paul Rappaport Award (2011).  He currently serves as an Associate Editor for IEEE T-ED, following his assignment with Microelectronics Reliability (Elsevier).

Tut26: Ferroelectric hafnium oxide based FeFETs - device reliability for non-volatile memories and beyond

Stefan Slesazeck (NaMLab)

The discovery of ferroelectricity in doped hafnium oxide that was firstly published in 2011 by Böschke et al. strongly increased the interest in ferroelectric memory devices. The polarization reversal in these thin films is used to store information in different device types. One of them is the ferroelectric field effect transistor (FeFET). The electrical characteristics of these devices are strongly influenced by the whole device design and material stack, rather than being dictated by the properties of the ferroelectric layer itself. Therefore, in this tutorial, I will first discuss the fundamental reliability aspects of ferroelectric hafnium oxide. In a second part I will shed some light on the specific reliability aspects of the different FeFET designs for their application in memory arrays and for the realization of unconventional computing paradigms.

Dr.-Ing. Stefan Slesazeck received the Ph.D. degree from TU Dresden in 2004. Since 2009 he is a Senior Scientist with NaMLab responsible for concept evaluation, hardware development, electrical characterization, and modeling of memories. On these topics, he is (co)-author of >200 publications and holds 10 US patents. His research interests comprise the development of novel memory devices with a focus on ferroelectric devices such as FeFETs and FTJs as well as research on novel computing paradigms based on these devices. Currently Stefan is coordinator of the H2020 BeFerroSynaptic project. Prior to joining NaMLab Stefan was a project leader for the predevelopment of new memory concepts and 3D devices with Qimonda, Dresden, Germany.

Tut27: RF Si CMOS and GaN Reliability for 5G/mmWave/RF Applications

Purushothaman Srinivasan (GlobalFoundries) and Donald A. Gajewski (Wolfspeed)

Si CMOS: 

This tutorial will provide a practical overview of the key reliability mechanisms along with the challenges faced by reliability engineers studying the reliability of 5G/WiFi and mmWave/RF applications implemented with silicon-based technologies. This tutorial reviews current progress in our understanding on key impact of short- and long-term stress on key RF metrics and new methodologies for RF reliability estimation in Front-End-Module circuits. The tutorial will also cover (1) Major reliability mechanisms  affecting the designs based on waveform analysis 2) Simulation and Modeling behavior under DC and RF conditions including self-heating using industry standard simulators, 3) Approach to the validation of the RF reliability models in silicon, 4) Long term reliability evaluation stress results and lifetime estimation under RF conditions and 5) An engineering approach on how to balance and optimize the Performance/Reliability trade-offs, providing a practical approach to Safe Operating Area will be presented. Throughout this tutorial, several examples of reliability stress data along with the models to support our methodology and conclusions will also be presented. 

III-V:
This tutorial will provide an overview of the failure mechanisms, reliability characterization techniques, intrinsic lifetime extrapolations, and qualification strategies for GaN devices for 5G/RF/mmW applications. Failure mechanisms include reverse piezo-electric GaN cracking, source-connected field plate electromigration driven by RF signals, ohmic contact degradation, humidity effects and charge trapping. Reliability characterization techniques include on-state (accelerated life test, DC- and RF-ALT, and high temperature operating life, DC- and RF-HTOL), off-state (high temperature reverse bias, HTRB) and accelerated gate bias. This tutorial will review approaches for constructing reliability and qualification plans for covering the RF I-V plane for various amplifier class modes and harsh operating environments.

Purushothaman Srinivasan (SP) is currently a Senior Member of Technical Staff (SMTS) working as a RF reliability team leader for CMOS Si technologies, at GLOBALFOUNDRIES, Malta, NY. He is currently focused on RF reliability in advanced CMOS nodes (45, 22, 14/12nm nodes). He was also a GLOBALFOUNDRIES assignee member at IBM, Albany until 2015.  His research areas include high-k metal gate, SiGe-based transistors, Negative Bias Temperature Instability, low frequency (1/f) noise and Random Telegraph Signals (RTS). From 2007-2012, he was a Research Staff Member at Texas Instruments, Dallas and was an adjunct professor in the MSE department at University of Texas, Dallas from 2010-2012. Since 2008, he has been an Executive Committee member of Dielectric Science and Technology Division at Electrochemical Society. He has been serving the IRPS transistor sub-committee since 2017 and served the Process Integration sub-committee in 2019.   Prior to joining TI, he obtained his PhD degree from IMEC, Leuven, Belgium and New Jersey Institute of Technology, Newark, NJ. He is also a senior member of IEEE, holds IEEE membership for 15 years, has edited five books, holds 5 patents, >20 invited talks authored and co-authored more than 150 international publications with over 1000 citations. His conference publications include top tier conferences at IEDM and VLSI. He currently as a reviewer for at least six journals, including the Journal of The Electrochemical Society and IEEE Transactions on Electron Devices and Electron Device Letters.

Tut28: Contactless Fault Isolation (CFI) techniques in die level Microelectronics Failure Analysis (FA) through the IC generations from micro to nanoscale nodes and Backside Power Distribution networks

Christian Boit (Technische Universitaet Berlin)

Contactless fault Isolation (CFI) on ICs started with a wide range of perspectives, from liquid crystal hot spot analysis to E beam probing. Over time, optical techniques became the most successful approaches that became even more established in the IC generations of flip chip and interconnect planarization. Infra red based CFI techniques like Photon Emission, Laser Stimulation inducing Delay Variation and/or Electro-optical probing have been very powerful to track almost each signal in Integrated Circuits.

This enormous success is challenged by the progress in IC technology to node dimensions smaller than 14nm. ResoIution can be improved by the use of shorter optical wavelengths but the price is drastical thinning of bulk silicon sub micron level plus a transparent solid immersion lens (SIL) on the top. In order to have CFI at any node size, a new approach reaching out to e beam probing based on very complex and meticulous preparation techniques is finding its way to meet the needs of single digit nanoscale node size IC technologies. 

The tutorial discusses also the critical points: Invasiveness of removal techniques, mechanical and thermal aspects, and how the individual design of a composition of global and local preparation techniques may make all the difference for success. It also presents a vision what fault isolation of an IC with Backside Power Distribution Networks could look like.

Christian Boit retired 2018 from Chair of Semiconductor Devices Department at Technische Universitaet Berlin, Germany. His research focuses on IC failure analysis (FA) and contactless fault isolation (CFI). In recent years, he was also investigating hardware security risks introduced by CFI. Chris started at Siemens Semiconductors 1986 and participated 1990 -1993 in IBM / Siemens DRAM project East Fishkill, NY. Later, he was Director of FA at Infineon Technologies until taking the university position in 2002. Chris is an active supporter of the FA community. He was co-founder and member of the board of directors of FA society EDFAS, served in many conference committees and was General Chair of major electronic device FA conferences ISTFA 2002 in US and ESREF 2014 in Europe.