Demonstrated a unified aging model framework, which not only can predict the traditional DC transistor aging, but also can accurately predict aging in various styles of circuits.

Ring-Oscillators (ROS) under arbitrary stress conditions are used to demonstrate model predictability after long-term stress approaching product use conditions

All data shown here is from the Intel-4 advanced FinFET technology, but the framework is validated against the other scaled technologies/geometries as well

Using measurement results and TCAD simulations, this work analyzes the effects of the deep collector P-Well doping on the I-V characteristic of a high-voltage lateral PNP

This work also provides guidelines for achieving an efficient collector.

Low-frequency AC response to evaluate damage due to Silicon-to-Package interaction

Original and novel method to classify ReRAM noise fluctuations using AI

Technique which can be extended to other technologies as well

Original and novel approach with rich experimental data and simulation results to predict the electro-chemical reliability performance of an IC

Technique can be extended to other packaging technologies as well

Extensive evaluation of the reliability of a 0.25 um AlGaN/GaN HEMT technology, based on thermal storage tests and DC life tests

Results showed degradation of current and transconductance related to Ni/Pt interdiffusion at the gate Schottky contact and electrochemical oxidation of the AlGaN

Reliability assessment of Multi-Bridge-Channel FET (MBCFET) adopted 3nm GAA technology, in comparison with 4 and 8nm FinFET technology

Gate Dielectric SOA concept introduces life model limited by not only Oxide MTTF, but also the lifetime associated drift in datasheet parameters Vth, RdsOn such that the device will stay within its operating specifications, as a result of electron trapping (or hole trapping which is shown to be not relevant with practical operating conditions)