IRPS Year-in-Review

Inside Program: Conference Program l Keynote Speakers l Tutorials
Workshops l Year in Review l Highlight Papers | Invited Speakers

The IRPS Reliability Year-in-Review (YiR) session consists of 3 presentations reviewing the past year's reliability work by experts in the field for areas of high interest. It is an excellent augmentation to the tutorial sessions immediately preceding, and attendees may obtain keen reliability insights in a short amount of time.

Speakers

YiR1: Neuromorphic: Brian Hoskins, NIST

YiR2: Dielectrics: Bonnie Weir, Broadcom

YiR3: GaN: Srabanti Chowdfury, Stanford Univ.

(YiR1) 15th April 3:00 PM - 3:50 PM

From the Mathematical Foundations to the Physical Models: A Year in Review of Neuromorphic Reliability

Brian Hoskins (NIST)

Abstract: Moving along in parallel with the emergence of ever stronger artificial intelligence, the development of next generation AI hardware which harnesses the unique properties of physical systems, beyond classical digital computing, has been continuously evolving. AI scientists, in the pursuit of lower energy costs and smaller model sizes, have already been willing to make compromises on model accuracy for improved performance in edge applications. In the case of novel AI hardware, trading off the reliability of digital systems for the reduced energy cost of analog and neuromorphic systems, presents new opportunities for exploring the same technology space as current efforts in edge inference. In this lecture, we will briefly review the foundations of modern AI from the perspective of loss function minimization, and explore how physical systems mathematically interact with this loss landscape. In doing so, we will explore how scientists this past year have been balancing the tradeoffs from device defects, analog noise, variability, and other phenomenon to develop next generation systems for AI inference as well as how to understand these developments using the mathematical tools employed by AI scientists.

Brian Hoskins is a research physicist in the Alternative Computing Group in the Nanoscale Device Characterization Division of the Physical Measurement Laboratory (PML) at the National Institute of Standards and Technology. He received both a B.S. and an M.S. in Materials Science and Engineering from Carnegie Mellon University and a Ph.D. in Materials from the University of California, Santa Barbara. For his doctoral research, he developed and characterized resistive switching devices for use in neuromorphic networks. Brian is working on CMOS integration of resistive switches for the development and characterization of intermediate scale neuromorphic networks.

(YiR2) 15th April 3:50 PM - 4:40 PM

Dielectric Breakdown: Advances in Characterization Techniques and Extrapolation to Use Conditions for Low and High-Voltage FETs

Bonnie Weir (Broadcom inc.)

Abstract: The engineering community has provided improvements in power, performance and area by developing device types such as nano-sheet field-effect transistors and Indium Gallium Zinc Oxide thin-film-transistors. Moreover, we have improved the gate and middle-end-of-line dielectric reliability in these various structures using methodology such as a novel circuit/measurement technique which allows collection of more statistically relevant data. Advances have been made in our ability to predict time-dependent dielectric breakdown despite process-driven variations. In addition, the drive to understand and predict dielectric reliability under actual field operation conditions has led to AC (even up to the GHz range) and drain-bias measurements, resulting in enhanced understanding of the complexity and applicability of these evaluation techniques. While transistors can function and meet performance specifications even after soft breakdown, some power MOSFETs fail performance metrics even before reaching the point of gate dielectric breakdown. Research achievements in Power MOSFET TDDB will be covered along with a new JEDEC standard, JEP194: Guideline for Gate Oxide Reliability and Robustness Evaluation Procedures for Silicon Carbide Power MOSFETs, published in 2023. Furthermore, we have made headway in interpreting the testing results of dielectrics in memory devices, which enables more accurate extrapolation from test to use conditions.

Bonnie E. Weir was born in Osaka, Japan. She received a B. A. in Physics from Swarthmore College in 1988 and a Ph. D. in Physics and Engineering Physics from Stevens Institute of Technology in 1993. She has explored ordered delta-doping at AT&T Bell Laboratories, soft breakdown of silicon oxynitrides at Lucent Technologies and electrostatic discharge protection at Agere Systems. She is currently a Master Engineer with Broadcom, Inc. in Allentown, Pennsylvania, where she works with designers to meet transistor-level and interconnect reliability rules while maintaining competitive design practices. With over forty publications, Weir holds 8 patents, has served on the IEDM Circuits, Reliability and Yield subcommittee and currently serves on the Reliability of Systems and Devices subcommittee. She chaired the IRPS Transistors subcommittee in 2022 and currently co-chairs the JEDEC taskgroup (142_6) on Gate Dielectric Breakdown. At IRPS2023, she co-chaired a workshop on FEOL/MOL reliability, and at IIRW2023, she served on a Reliability Experts Forum. She enjoys volunteer work at Geneva College, and serves as the Secretary of the Board of Trustees.

(YiR3) 15th April 4:40 PM - 5:50 PM

The exciting era of compact electronics with Gallium Nitride technology

Srabanti Chowdfury (Stanford Univ.)

Abstract: We find ourselves in an era marked by a global push towards electrification, with a particular emphasis on reliability. The ongoing transformation in transportation, matching the impact of the internal combustion engine, is complemented by the increasing intelligence and affordability of smart devices across various domains, fueled by the Internet of Things (IoT). The advent of robotics and autonomous vehicles promises to revolutionize our daily lives. Within this technological surge, the commitment to achieving a carbon-free energy system by 2050 underscores the need for highly reliable energy-efficient electronics at every level. A pivotal path that Gallium Nitride and Silicon Carbide technology have demonstrated is higher power density at the device level that can be tranlasted towards system level as well. The roadmap to success hinges on the successful integration of GaN and other WBGs into circuit boards to drive diverse applications. However, the journey has not been seamless, particularly with GaN transistors, which have not provided a plug-and-play experience. Realizing the theoretically-predicted efficiencies from a WBG-driven system often necessitates modifications, ranging from adjustments in power modules to complete circuit topology reinventions. Operating conditions optimized for WBG devices can introduce risks, with parasitic devices in integrated circuits posing threats such as latch-up, electrostatic discharge (ESD), and other high-field phenomena like avalanche. Understanding and addressing these challenges are crucial for ensuring the functional security of systems, especially under extreme operating and environmental conditions. The success of gallium nitride technology in RF has been steady and paved its way towards 5G/6G alongside Silicon. Adding more power density at higher frequencies at higher operating temperatures, without degrading the efficinciy of amflifiers has been the key driver that sets GaN apart from its competitors. Need for more power density has paved the way for exploration into hetergenous integration with diamond and AlN for thermal management.

Professor Srabanti Chowdhury, of the Electrical Engineering department, also affiliated by courtesy, with the Materials Science and Engineering, at Stanford University, specializes in the wideband gap (WBG) and ultra-wide bandgap (UWBG) materials and device engineering. Her research focuses on energy-efficient system architecture for power and RF applications, particularly emphasizing thermal management. She earned her M.S. in June 2008 and Ph.D. in December 2010 in Electrical and Computer Engineering from the University of California, Santa Barbara. In recognition of her outstanding work on diamond integration with GaN and SiC, resulting in very low thermal boundary resistances for thermal management, Prof. Chowdhury received the 2023 Technical Excellence Award from the Semiconductor Research Society (SRC). Her achievements also include the 2020 Alfred P. Sloan Fellowship in Physics and the 2016 Young Scientist Award at the International Symposium on Compound Semiconductors (ISCS). Earlier in her career, she was honored with the DARPA Young Faculty Award, NSF CAREER Award, and AFOSR Young Investigator Program (YIP), all in 2015.
Prof. Chowdhury's significant contributions to the field encompass 6 book chapters, 120 journal papers, 150 conference presentations, and 26 issued patents. Actively engaged in IEEE conference committees, including IRPS and VLSI Symposium, she serves on the executive committee of IEDM. Since 2021, she has been a senior fellow at the Precourt Institute for Energy at Stanford. She became an IEEE fellow in 2024 for her contributions to wide bandgap semiconductor devices and technology.