IRPS

2021 IRPS & IEW Tutorials

Tutorial sessions offer a supreme overview of reliability in semiconductors, circuits, systems unavailable at any other venue at a tremendous value. IRPS conference has a very long history of dedicating two full days to the Tutorials sessions. Since 2011, IRPS conference has offered 129 tutorial 90 minute sessions with an average of over 21 unique sessions per year delivered by industry, academia, and government experts. IRPS tutorial program is designed for the newcomer, the informed, and the expert so whether one is a university student, a field practitioner, or an IEEE fellow, all may gain knowledge in their area or an adjacent one.

 Abstract1st Presenter2nd Presenter
Tut1Reliability Challenges with 3D Integration of Semiconductor PackagingEnamul Kabir - Intel
Tut2Practical Applications of Bayesian ReliabilityYan Liu - Medtronic
Tut3Methodologies for Device Reliability Testing: From DC to Sub-nsYi Zhao - Zhejiang University
Tut45G/mmW/RF- Silicon

5G/mmW/RF-GaN
Fernando Guarin - Globalfoundries Don Gajewski - Wolfspeed
Tut5Neuromorphic ComputingBrian Hoskins - NIST
Tut6Calculation of Terrestrial Cosmic Ray Displacement DamageMelanie Raine - CEA
Tut7Understanding and Challenges of MOL/BEOL TDDB ReliabilityAndrew Kim - Intel
Tut8GaN ReliabilityEnrico Zanoni - University of Padova
Tut9High-K Dielectrics on Non Silicon SemiconductorsChadwin Young - University of Texas - Dallas
Tut10Advanced 3D Flash Memory ArchitecturesHang Ting Lue - Macronix
Tut11Magnetic Resonance TechniquesMark Anders - NIST
Tut12DRAM Reliability OverviewHokyung Park - SK hynix
Tut13Hot-carrier Degradation in Si Devices – from Experimental Observations to Accurate Physical ModelingStanislav Tyaginov - IMEC
Tut14Metal reliability for advanced interconnectsOlalla Varela - IMEC
Tut15AutomotiveAndreas Aal - Volkswagen

(in cooperation with IEW)
Oliver Aubel - Globafoundries
Tut16Reliability and Performance Limiting Defects in 4H SiC Metal Oxide Semiconductor Field Effect TransistorsPatrick Lenahan- Penn State University
Tut17Application and characterization of CMOS cryogenic electronicsPragya Shrestha - NIST
Tut18Electronic Design Automation (EDA) Solutions for Latch-up Verification in CMOS and HV TechnologiesMichael Khazhinsky - Silicon Labs
(in cooperation with IEW)
Tut19EOS, ESD, Transient, AMR, EIPD, Robustness, Aging - Do All of These Pieces go to the Same Puzzle?Hans Kunz - Texas Instruments

(in cooperation with IEW)
Tut20Exploring Relation of ESD and EMC: Tests, Events to Damage, Failure Types, and Co-Design ApproachesAlan Righter - Analog Devices
Tut21FinFET Self-heating: Measurements, Concerns and ApplicationsZakariae Chbili - Intel

(in cooperation with IEW)
Tut22Full chip CDM ESD VerificationMelanie Etherton - NXP