2019 IRPS Keynote Presentations

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Keynote 1: Abundant-Data Computing: The N3XT 1,000X

Professor Subhasish Mitra, Stanford University

8:35 AM, Tuesday April 2


Coming generations of information technology will process unprecedented amounts of loosely-structured data, including streaming video and audio, natural languages, real-time sensor readings, contextual environments, or even brain signals. The computation demands of these abundant-data applications, such as deep learning, far exceed the capabilities of today’s electronics, and cannot be met by isolated improvements in transistor technologies, memories, or integrated circuit (IC) architectures alone. Transformative NanoSystems, which leverage salient features of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented performance and energy efficiency.

The N3XT (Nano-Engineered Computing Systems Technology) approach overcomes these challenges through recent advances across the computing stack: (a) new logic devices using nanomaterials such as one-dimensional carbon nanotubes (and two-dimensional semiconductors) for high performance and energy efficiency; (b) high-density non-volatile resistive memories; (c) ultra-dense (e.g., monolithic) three-dimensional integration of logic and memory with fine-grained connectivity; (d) new IC architectures for computation immersed in memory; and, (e) new materials technologies and their integration for efficient heat removal. In addition, special techniques to overcome imperfections, variations and reliability challenges in such logic and memory technologies are essential.

N3XT hardware prototypes represent leading examples of transforming scientifically-interesting nanomaterials and nanodevices into actual NanoSystems. Compared to conventional approaches, N3XT architectures promise to improve the system-level energy-delay-product of abundant-data applications significantly, in the range of three orders of magnitude. Such massive benefits enable new frontiers of applications for a wide range of computing systems, from embedded systems all the way to the cloud.


Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University, where he directs the Stanford Robust Systems Group and co-leads the Computation focus area of the Stanford SystemX Alliance. He is also a faculty member of the Wu Tsai Neurosciences Institute at Stanford. Prof. Mitra holds the Carnot Chair of Excellence in Nanosystems at CEA-LETI in Grenoble, France. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation.

Prof. Mitra’s research interests range broadly across robust computing, nanosystems, VLSI design, validation, test and electronic design automation, and neurosciences. He, jointly with his students and collaborators, demonstrated the first carbon nanotube computer and the first three-dimensional nanosystem with computation immersed in data storage. These demonstrations received wide-spread recognitions (cover of NATURE, Research Highlight to the United States Congress by the National Science Foundation, highlight as “important, scientific breakthrough” by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post and numerous others worldwide). His earlier work on X-Compact test compression has been key to cost-effective manufacturing and high-quality testing of almost all electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools.

Prof. Mitra’s honors include the ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation (a test of time honor), the Semiconductor Research Corporation’s Technical Excellence Award, the Intel Achievement Award (Intel’s highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers).  He and his students published several award-winning papers at major venues: ACM/IEEE Design Automation Conference, IEEE International Solid-State Circuits Conference, ACM/IEEE International Conference on Computer-Aided Design, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors “for being important to them during their time at Stanford.”

Keynote 2: The Era of Hyperscaling in Electronics

Professor Suman Datta, University of Notre Dame

9:20 AM, Tuesday April 2


In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometer, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. In this talk, I will discuss how electronics is poised to enter a new, third, era of scaling – hyperscaling – in which resources are added in a flexible way when needed to meet the demands of data abundant workloads. This era will be driven by advances in extremely low power beyond-Boltzmann transistors, embedded non-volatile memories, hybrid devices with merged logic and memory functionalities, monolithic three-dimensional integration, and heterogeneous integration techniques.


Suman Datta is the Frank M. Freimann Chair Professor of Engineering at the University of Notre Dame. Prior to that, he was a Professor of Electrical Engineering at The Pennsylvania State University, University Park, from 2007 to 2011. From 1999 till 2007, he was in the Advanced Transistor Group at Intel Corporation, Hillsboro, where he developed several generations of high-performance logic transistor technologies including high-k/metal gate, Tri-gate and non-silicon channel CMOS transistors. His research group focuses on emerging device concepts that support and enable new computational models. He is a recipient of the Intel Achievement Award (2003), the Intel Logic Technology Quality Award (2002), the Penn State Engineering Alumni Association (PSEAS) Outstanding Research Award (2012), the SEMI Award for North America (2012), IEEE Device Research Conference Best Paper Award (2010, 2011) and the PSEAS Premier Research Award (2015).  He is a Fellow of IEEE and the National Academy of Inventors (NAI). He has published over 300 journal and refereed conference papers and holds 175 patents related to advanced semiconductors. He is the Director of a multi-university advanced microelectronics research center, called the ASCENT, funded by the Semiconductor Research Corporation (SRC) and the Defense Advanced Research Projects Agency (DARPA). He will serve as the Technical Program Chair of the 2019 IEEE International Electron Device Meeting (IEDM).