Plenary Keynote-I (Virtual IRPS 2020)
Dr. Mike Mayberry - Intel

Title: The Future of Compute: Reliability and Resiliency in the era of Data Transformation

Abstract: The digital transformation continues to gain momentum and is changing the shape of business, industry and consumers around the world. This transformation is characterized by continued strong demand for compute at all points in the network – at the core, the edge, and at the endpoints. Data continues to grow at an exponential rate and not only drives the compute requirements, but also requires efficient solutions for movement and storage of data that is critical for overall performance. From device to cloud, new applications and use cases are continuously emerging. This transformation demands that we adapt our thinking and move from a hardware/program centric to a data/information centric approach, and to embrace new ways to compute. To keep pace in this dynamic environment, Moore’s Law and its impact have become more relevant than ever. The continued dimensional, materials and device scaling drives a renewed focus on the fundamental reliability physics of devices and materials, while novel architecture integration schemes and large-scale system design innovation motivates a more comprehensive understanding of resiliency at all levels of the system.


Dr. Michael (Mike) C. Mayberry is the chief technology officer at Intel Corporation. He is a senior vice president and general manager of Technology Development, where he is responsible for the research, development and deployment of next-generation silicon logic, packaging and test technologies that will produce future Intel products.

Since joining Intel in 1984 as a process integration engineer, Mayberry has held a variety of positions. As part of the California Technology Development team, he developed EPROM, flash and logic wafer fabrication processes. In 1994, he moved to Sort Test Technology Development, responsible for roadmaps and development of test processes for Intel microprocessors. In 2005, he moved to Components Research and was responsible for research to enable future process options for Intel’s technology development organizations. In 2015, he moved to Intel Labs and became responsible for Intel’s product-driven research. In 2018, he moved to the Technology Development group at Intel.

Mayberry received his bachelor’s degree in chemistry and mathematics from Midland College and his Ph.D. in physical chemistry from the University of California, Berkeley.​

Mike Mayberry

Plenary Keynote-II (Virtual IRPS 2020)
Dr. Oliver Häberlen - Infineon Technologies Austria AG

Title: Power Semiconductor Reliability – An Industry Perspective on Status and Challenges

Abstract: Power transistors are an inevitable key component of nearly every power electronic system enabling the path to a greener environment through increased conversion efficiency. Silicon based power transistors are established on the market since more than half a century and the reliability and quality of those devices has matured to failure levels in the sub ppm range. The base for this achievement was a deep understanding of all the failure modes and their corresponding lifetime models.
The new wide band gap power semiconductor materials SiC and GaN that have entered the market during the past respective this decade are on much earlier points along a similar learning curve. It will be shown that the methodology how to qualify a power semiconductor technology remains essentially unchanged for the new devices, but of course all the new material and device specific failure modes need to be understood and modelled. The most important past learnings will be shown in this talk.
So everything is solved for the established silicon technologies? Also here we face new challenges due to the ever continuing pressure for cheaper devices mostly addressed by device shrinks. Pushing the devices closer and closer to their physical limits of course also requires refining and improving the established models in order to tailor the exactly right amount of safety margin. Additionally increasing power and current densities on die level require new package concepts leading to potential new failure modes.
Finally, we will conclude with some examples on a general trend observed: Fitting the devices as good as possible to the target applications and their respective requirements is leading to the need for an increased focus on application reliability testing.


Dr. Oliver Häberlen received his M.S. and Ph.D. degree in physics from the University of Munich and Technical University of Munich respectively.
He is currently employed with Infineon Technologies Austria AG as a Senior Principal for Power Transistor Technology and heading the group for advanced technology concepts evaluating future silicon and wide band gap (SiC, GaN) power device concepts for improved energy conversion solutions. His research areas include low and medium voltage trench power MOSFETs, high voltage super junction devices, GaN power devices and power device reliability.
He is a senior member of IEEE and member of the IEEE EDS Power Devices and ICs Technical Committee. He also served as Technical Committee member for IEDM (International Electron Devices Meeting) and ISPSD (International Symposium on Power Semiconductor Devices and ICs) and is the General Chair of the ISPSD conference in 2020. He is author and co-author of over 100 international patents and patent applications in the field of power semiconductors.


Plenary Keynote-III (Virtual IRPS 2020)
Dr. Gianluca Boselli - Texas Instruments

Title: Power scalability challenges in High-Voltage ESD Design

Abstract: The criticality of Analog Technologies has significantly increased over the last decade, due to the phenomenal success of portable consumer electronics, which require multiple analog functions to be implemented in the same chip. The relatively recent push towards society “electrification” (electric cars, smart power grids, IoT) is driving the need for higher and higher voltage applications together with a plethora of functional and safety requirements, which pose significant challenges in terms of ESD Design. This paper discusses these challenges, with special emphasis on the perspective of power scalability.


Gianluca Boselli completed his master’s in EE at the University of Parma, Italy, in 1996. In 2001, he completed his PhD at the University of Twente, The Netherlands; where he worked on high current phenomena in CMOS technologies. In 2001, he joined Texas Instruments, Inc., Dallas, Texas; where he focused on ESD and latch-up development for advanced CMOS technologies, with particular emphasis on process and modeling aspects. In 2007, his responsibilities extended into ESD development of Texas Instruments’ analog technologies portfolio. He is currently managing both ESD and Spice Modeling Teams.
He authored several papers in the area of ESD and latch-up. He presented his work at major conferences, including EOS/ESD Symposium, IEDM, and IRPS. He has also presented many invited tutorials and papers at various conferences, including EOS/ESD Symposium, IRPS, IEDM, ESREF, IEW, and RCJ.
Dr. Boselli has been the recipient of the best paper award on behalf of Microelectronics Reliability Journal in 2000. He received the best paper award at the EOS/ESD Symposium 2002. He also received the Outstanding Symposium award at the EOS/ESD Symposium in 2002, 2006, and 2010.
Dr. Boselli served multiple times as sub-committee chair for technical program committees (TPC) of EOS/ESD Symposium, IEDM, IRPS, IEW, and ESREF. He served as moderator and panelist in many workshops in ESD and latch-up area.
Dr. Boselli has served as TPC chair at the EOS/ESD Symposium 2006, vice-general chair at the EOS/ESD Symposium 2007, and general chair at the EOS/ESD Symposium 2008.
He is currently a member of the board of directors of EOS/ESD Association, Inc
Dr. Boselli is an IEEE senior member and holds over twenty patents with several pending.
Dr. Boselli serves in the editorial board of the IEEE Transactions on Device and Materials Reliability (T-DMR).