2018 IRPS Keynote Presentations

First Keynote: The Road to Resilient Computing in Autonomous Driving is Paved with Redundancy

Dr. Nirmal Saxena, NVIDIA

8:45 AM, Tuesday March 13th

Abstract: Deep neural networks use the computational power of massively parallel processors in applications such as autonomous driving. Autonomous driving demands resiliency (as in safety and reliability) and trillions of operations per second of computing performance to process sensor data with extreme accuracy. This keynote examines various approaches to achieve resiliency in autonomous cars and makes the case for design diversity based redundancy.

Biography: Nirmal R. Saxena is currently a distinguished engineer at NVIDIA and is responsible for HPC and automotive resilient computing. From 2011 through 2015, Nirmal was associated with Inphi Corp as CTO for Storage & Computing and with Samsung Electronics as Sr. Director working on fault-tolerant DRAM memory and storage array architectures. During 2006 through 2011, Nirmal held roles as a Principal Architect, Chief Server Hardware Architect & VP at NVIDIA.  From 1991 through 2009, he was also associated with Stanford University’s Center for Reliable Computing and EE Department as Associate Director and Consulting Professor respectively. During his association with Stanford University, he taught courses in Logic Design, Computer Architecture, Fault-Tolerant Computing, supervised six PhD students and was co-investigator with Professor Edward J. McCluskey on DARPA’s ROAR (Reliability Obtained through Adaptive Reconfiguration) project.  Nirmal held senior technical and management positions at Alliance Semiconductors, Chip Engines, Tiara Networks, Silicon Graphics, HaL Computers, and Hewlett Packard.

Nirmal received his Ph.D. EE degree (1991) from Stanford University.  He is a Fellow of the IEEE (2002) and was cited for his contributions to reliable computing.

Second Keynote: Reliable Ultra-Low Energy Security Circuit Primitives for IoT Edge Systems

Dr. Sanu Mathew, Intel Corporation

9:30 AM, Tuesday March 13th

Abstract: Low-area energy-efficient security primitives are key building blocks for enabling end-to-end content protection, user authentication and data security in IoT platforms. This talk describes the design of reliable security circuit primitives with optimal arithmetic for seamless integration into area/battery constrained IoT systems: 1) A 2040-gate AES accelerator achieving 289Gbps/W efficiency in 22nm CMOS, 2) Hardened hybrid Physically Unclonable Function (PUF) circuit to generate a 100% stable encryption key. The talk will also discuss design issues related to side-channel leakage of embedded secret keys, and how they may be addressed during design of encryption circuits. We will also discuss the effect of aging on PUF circuits and techniques to handle aging issues over the lifetime of the die.

Biography: Sanu Mathew is a Senior Principal Engineer with the Circuits Research Labs at Intel Corporation, Hillsboro, Oregon, where he leads research and development of energy-efficient hardware accelerators for encryption and security. Sanu obtained his Ph.D. degree in Electrical and Computer Engineering from State University of New York at Buffalo in 1999. He holds 41 issued patents, with another 63 patents pending and has published over 77 conference/journal papers. He has been with Intel for the past 18 years. Sanu is a Fellow of the IEEE.