Abstract:
Coming generations of information technology will process unprecedented amounts of loosely-structured data, including streaming video and audio, natural languages, real-time sensor readings, contextual environments, or even brain signals. The computation demands of these abundant-data applications, such as deep learning, far exceed the capabilities of today’s electronics, and cannot be met by isolated improvements in transistor technologies, memories, or integrated circuit (IC) architectures alone. Transformative NanoSystems, which leverage salient features of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented performance and energy efficiency.
The N3XT (Nano-Engineered Computing Systems Technology) approach overcomes these challenges through recent advances across the computing stack: (a) new logic devices using nanomaterials such as one-dimensional carbon nanotubes (and two-dimensional semiconductors) for high performance and energy efficiency; (b) high-density non-volatile resistive memories; (c) ultra-dense (e.g., monolithic) three-dimensional integration of logic and memory with fine-grained connectivity; (d) new IC architectures for computation immersed in memory; and, (e) new materials technologies and their integration for efficient heat removal. In addition, special techniques to overcome imperfections, variations and reliability challenges in such logic and memory technologies are essential.
N3XT hardware prototypes represent leading examples of transforming scientifically-interesting nanomaterials and nanodevices into actual NanoSystems. Compared to conventional approaches, N3XT architectures promise to improve the system-level energy-delay-product of abundant-data applications significantly, in the range of three orders of magnitude. Such massive benefits enable new frontiers of applications for a wide range of computing systems, from embedded systems all the way to the cloud.
Biography:
Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University, where he directs the Stanford Robust Systems Group and co-leads the Computation focus area of the Stanford SystemX Alliance. He is also a faculty member of the Wu Tsai Neurosciences Institute at Stanford. Prof. Mitra holds the Carnot Chair of Excellence in Nanosystems at CEA-LETI in Grenoble, France. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation.
Prof. Mitra’s research interests range broadly across robust computing, nanosystems, VLSI design, validation, test and electronic design automation, and neurosciences. He, jointly with his students and collaborators, demonstrated the first carbon nanotube computer and the first three-dimensional nanosystem with computation immersed in data storage. These demonstrations received wide-spread recognitions (cover of NATURE, Research Highlight to the United States Congress by the National Science Foundation, highlight as “important, scientific breakthrough” by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post and numerous others worldwide). His earlier work on X-Compact test compression has been key to cost-effective manufacturing and high-quality testing of almost all electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools.
Prof. Mitra’s honors include the ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation (a test of time honor), the Semiconductor Research Corporation’s Technical Excellence Award, the Intel Achievement Award (Intel’s highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He and his students published several award-winning papers at major venues: ACM/IEEE Design Automation Conference, IEEE International Solid-State Circuits Conference, ACM/IEEE International Conference on Computer-Aided Design, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors “for being important to them during their time at Stanford.”
Abstract:
In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometer, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. In this talk, I will discuss how electronics is poised to enter a new, third, era of scaling – hyperscaling – in which resources are added in a flexible way when needed to meet the demands of data abundant workloads. This era will be driven by advances in extremely low power beyond-Boltzmann transistors, embedded non-volatile memories, hybrid devices with merged logic and memory functionalities, monolithic three-dimensional integration, and heterogeneous integration techniques.
Biography:
Suman Datta is the Frank M. Freimann Chair Professor of Engineering at the University of Notre Dame. Prior to that, he was a Professor of Electrical Engineering at The Pennsylvania State University, University Park, from 2007 to 2011. From 1999 till 2007, he was in the Advanced Transistor Group at Intel Corporation, Hillsboro, where he developed several generations of high-performance logic transistor technologies including high-k/metal gate, Tri-gate and non-silicon channel CMOS transistors. His research group focuses on emerging device concepts that support and enable new computational models. He is a recipient of the Intel Achievement Award (2003), the Intel Logic Technology Quality Award (2002), the Penn State Engineering Alumni Association (PSEAS) Outstanding Research Award (2012), the SEMI Award for North America (2012), IEEE Device Research Conference Best Paper Award (2010, 2011) and the PSEAS Premier Research Award (2015). He is a Fellow of IEEE and the National Academy of Inventors (NAI). He has published over 300 journal and refereed conference papers and holds 175 patents related to advanced semiconductors. He is the Director of a multi-university advanced microelectronics research center, called the ASCENT, funded by the Semiconductor Research Corporation (SRC) and the Defense Advanced Research Projects Agency (DARPA). He will serve as the Technical Program Chair of the 2019 IEEE International Electron Device Meeting (IEDM).
Abstract:
A variety of wireless devices ranging from cell phones to smart hardware and IoT devices have emerged and will continue to develop rapidly, together with the emerging new technologies such as IoT and 5G wireless. While wireless communication enables convenient connections of the devices, it also makes them inherently vulnerable to electromagnetic interference. Any radio frequency (RF) antenna used as a radio receiver can easily pick up the unintended electromagnetic noise from digital circuits, resulting in RF interference. Unlike conventional EMI issues, RF interference usually deals with noise at a much lower level and does not have standards or regulations to follow. In this talk, fundamentals of RF interference issues in wireless devices will be introduced. Challenges and progress in noise source characterization, understanding of coupling mechanisms, and mitigation solutions will be discussed and illustrated using real-world examples. RF interference and ESD are two dominant design issues in wireless devices. It will be shown that ESD protection circuits could be a source for RF interference. Modulation and intermodulation generated in these circuits could result in the noise components falling into the receiver band and thus degrade the performance of the receiver. Effort in modeling and characterizing this problem will be proposed.
Biography:
Jun Fan received his B.S. and M.S. degrees in Electrical Engineering from Tsinghua University, Beijing, China, in 1994 and 1997, respectively. He received his Ph.D. degree in Electrical Engineering from the University of Missouri-Rolla in 2000. From 2000 to 2007, he worked for NCR Corporation, San Diego, CA, as a Consultant Engineer. In July 2007, he joined the Missouri University of Science and Technology (formerly University of Missouri-Rolla), and is currently the Cynthia Tang Missouri Distinguished Professor in Computer Engineering and Director of the Missouri S&T EMC Laboratory. Dr. Fan also serves as the Director of the National Science Foundation (NSF) Industry/University Cooperative Research Center (I/UCRC) for Electromagnetic Compatibility and Senior Investigator of Missouri S&T Material Research Center. His research interests include signal integrity and EMI designs in high-speed digital systems, dc power-bus modeling, intra-system EMI and RF interference, PCB noise reduction, differential signaling, and cable/connector designs. In the IEEE EMC Society, Dr. Fan served as the Chair of the TC-9 Computational Electromagnetics Committee from 2006 to 2008, the Chair of the Technical Advisory Committee from 2014 to 2016, and a Distinguished Lecturer in 2007 and 2008. He currently is an associate editor for the IEEE Transactions on Electromagnetic Compatibility and IEEE EMC Magazine. Dr. Fan received an IEEE EMC Society Technical Achievement Award in August 2009. He is an IEEE fellow.
Abstract:
This Invited Talk will explain in detail, recommendations for testing components to the IEC 61000-4-2 standard. While components are not completed systems, OEMs still ask their vendors to test components outside the system according to this standard. There is no real guidance for this in the IEC 61000-4-2 standard and results are not repeatable. This talk aims to give guidance to those who have to conduct the test regardless. The talk will also review the similarities and differences between testing to the IEC 61000-4-2 standard and the HMM standard practice. The hurdles and pitfalls to system level testing is shown and best practices are outlined. This talk also reviews several controlled experiments to determine the amount of variability that is typical in this type of test. One of the experiments is a round robin study with 10 labs and four types of components. Its findings will be summarized. A second experiment was conducted with one part, one operator and different equipment. Finally, a third experiment looked at changing different parameters of the test set up too see if the results would be impacted.
Biography:
Doctor Kathleen Muhonen is currently an ESD Engineer at Qorvo in Greensboro, NC. She is involved in ESD on-chip protection for mobile and millimeter wave applications. She is also heavily involved with system level testing and helped standardize IEC testing of RF components. Kathleen is heavily involved in ESD instrumentation for better ESD characterization of clamps and materials. Previously she was responsible for RF characterization and model support for SOI and Gallium Arsenide technologies for power amplifiers, switches and antenna tuners. She has also done extensive work on developing state of the art harmonic characterization of semiconductors, improving de-embedding techniques of large scale switches and development of an Envelope Tracking Load-pull characterization bench. Kathleen’s previous experience includes assistant professor at Penn State Erie, linearization design for base stations at Hewlett Packard, power amplifier design at Lockheed Martin and GE Aerospace. Kathleen has served as a member of the ESD Association and sat on all device testing standards committees, including serving as past TLP and HMM workgroup chairs. She has also served on the Board of Directors as curricular implementation chair. Her involvement in round robin testing for TLP, VF-TLP and IEC Component Testing has generated several papers presented at the EOS/ESD Symposium over the last decade. Kathleen received her BSEE degree from Michigan Technological University in 91, a MSEE from Syracuse University in 94 and a Ph.D.EE from Penn State University in 99.
Abstract:
In CMOS ICs, latchup is formed by the parasitic p-n-p-n structure between power lines of VDD and VSS. Such parasitic p-n-p-n structure is inherent in the bulk CMOS technology. The parasitic p-n-p-n structure could be accidentally triggered on by external glitches or transient noises to generate a low-impedance path between the power lines. When latchup was triggered on, CMOS ICs were often burned out seriously by the latchup-generated heat. Therefore, latchup presentation is one of major reliability topics in CMOS ICs, especially realized in bulk CMOS technology. In this talk, a brief background of latchup in CMOS ICs is given. The methodology to extract compact layout rules used to prevent latchup occurrence on the I/O cells is introduced. Even if the I/O cells of a CMOS IC are free from latchup, the core circuits in the CMOS ICs will be still sensitive to latchup issue. The reasons to cause latchup occurrence on the core circuits are explained, including the transient-induced latchup during system-level ESD or FET testing. To further improve latchup immunity of CMOS ICs but without enlarging the spacing/distance in the chip layout, a novel concept of “active guard ring” and its corresponding circuit implementation will be addressed. Additional latchup events on the circuits with different power domains, such as HV and LV blocks, I/O PMOS and core PMOS, PMOS and varactor, will be discussed. Finally, the low holding voltage of the on-chip ESD protection device used in the power-rail ESD clamp may also cause latchup-like failure. The solutions to overcome such latchup-like issue, especially in HV applications, will be mentioned. Latchup prevention in CMOS ICs is not only the process issue but also highly dependent to the layout and design issue, which has been an important topic that the IC designers need to know.
Biography:
Ming-Dou Ker received the Ph.D. degree from National Chiao-Tung University, Hsinchu, Taiwan, in 1993. He worked as the Department Manager with the VLSI Design Division, Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan. During 2012-2015, he was the Dean of the College of Photonics, National Chiao-Tung University (NCTU), Taiwan. Now, he has been the Distinguished Professor in the Institute of Electronics, National Chiao-Tung University, Taiwan. Currently, he is also serving as the Director of the Biomedical Electronics Translational Research Center (BETRC), NCTU, working on biomedical electronics translational projects.
In the technical field of reliability and quality design for microelectronic circuits and systems, he has published over 560 technical papers in international journals and conferences. He has proposed many solutions to improve the reliability and quality of integrated circuits, which have been granted with hundreds of U.S. patents. He had been invited to teach and/or to consult the reliability and quality design by hundreds of design houses and semiconductor companies in the worldwide IC industry. His current research interests include the circuits and systems for biomedical applications, as well as circuit-related reliability issue.
Professor Ker has served as member of the Technical Program Committee and the Session Chair of numerous international conferences for many years, including IEEE Symposium on VLSI Circuits and IEEE International Solid-State Circuits Conference. He ever served as the Associate Editor for the IEEE Transactions on VLSI Systems, 2006-2007. He served as the Distinguished Lecturer in the IEEE Circuits and Systems Society (2006–2007) and in the IEEE Electron Devices Society (2008–2018). He was the Founding President of Taiwan ESD Association. Currently, he is serving as an Editor for the IEEE Transactions on Device and Materials Reliability, and an Associate Editor for the IEEE Transactions on Biomedical Circuits and Systems. Professor Ker has been a Fellow of the IEEE since 2008.
