Reliability Year in Review
The 2017 IRPS Reliability Year in Review will take place on Monday, April 3rd at 2:30 – 5:00 pm.
|FinFET Reliability||Aaron Thean, NUS (formerly imec)|
|GaN RF and Power Transistor Reliability||Matteo Meneghini, U. Padova|
|Memory Technology Reliability||Bob Gleixner, Micron|
FinFET Reliability Year-in-Review and What’s in Store for the Post-FinFET Era
Over the last decade, CMOS logic technologies have incorporated several material disruptions. Advanced CMOS made the transition from Poly-SiON to High-k metal gate (HKMG) process about 10 years ago, for 45nm and 32nm/28nm planar CMOS transistors developed from 2007 to 2009, respectively. The efforts to bring these technologies to high-volume manufacturing accelerated our learning on gate-stack reliability, especially the role of thermal budget management on the replacement metal-gate process. There are major influences of gate PBTI and NBTI due to the device integration scheme like dopant activation and silicidation. For example, “high-k-first” and “high-k-last” gate stacks showed different reliability potentials. However, with process and integration schemes, we found solutions to engineer both stacks to meet requirements.
The next disruption came quickly as we transitioned from planar to FinFET technologies in 2011, with Intel’s 22nm CMOS. This coincided with the capabilities of Atomic Layer Deposition (ALD) technologies for the the HKMG process. The lessons learnt on managing BTI impact did carried forward, but we now contend with new influences due to a different dielectric-crystalline interface of the fin sidewalls and the process challenges of a largely vertically oriented gate structure. We saw that ALD material improvements helped us overcome some of the issues. However, with increased current densities and aggressive dimensional scaling, hot-carrier and device self-heating rose to top of the issue list. Following the current success of 14nm/16nm FinFET technologies, we will soon be seeing the 3rd generation FinFET technologies with upcoming10nm and 7nm CMOS, in the coming two years. However, there are still really few knobs to overcome these top issues at the material or process levels. Except, at the circuit design or system levels through engineering the use conditions.
The next disruptions may come at or after 5nm CMOS targeted for 2020. With the need for more performance, new materials like SiGe fins are being considered for integration, or stacked Nanowires. We see exciting new reliability understanding and opportunities brought forth with these new materials and structures. Beyond FinFETs and beyond Si, we will need to prepare for low-thermal budget processes (E.g. for III-V, Ge). Encouragingly in recent years, we have gained significant new insights towards reliable low-thermal budget gate stacks. This will pave the way needed to realize the integration of these new materials for the Fin or Nanowire devices. In this presentation, we will review this evolution of understanding in reliability physics driven by this relentless revolution of device and material architectures to continue Moore’s law.
Aaron Thean is a Professor of Electrical and Computer Engineering at the National University of Singapore (NUS), since May 2016. His current research interests involve Heterogeneous Integration of Nano-systems and Hybrid-Flexible Electronics. He is the Director of NUS’ new central Nanofabrication Center. Besides his NUS responsibilities, Aaron is a senior consultant to imec, serves on the Scientific Advisory Board for the NUS-MIT research alliance, SMART-LEES, and he is an Editor of IEEE Electron Device Letters. Prior to his transition to NUS, Aaron was the Vice President of Logic Technologies and the Director of the Logic Devices Research at IMEC. From 2011 to 2016, he directed the research and development of device technologies ranging from ultra-scaled FinFETs to III-V/Ge Channels, emerging nano-device architectures, logic spintronics, and novel materials. Before 2011, Aaron was with Qualcomm’s CDMA technologies in San Diego, California. Before Qualcomm, Aaron was the Device Manager at IBM East Fishkill New York, where he led his team to develop the industry’s first gate-first metal-gate 28-nm and 32-nm low-power bulk CMOS technologies. The technology was successfully commercialized by IBM’s foundry partners and enabled some of today’s most successful mobile devices. Aaron started his industry career at Freescale Semiconductor (and Motorola) where he did research on many novel devices that included Strained-Si-On-Silicon, FinFETs, FDSOI, and Nanocrystal Flash Memory. Aaron graduated from University of Illinois at Champaign-Urbana, USA, where he received his B.Sc, M.Sc, and Ph.D degrees in Electrical Engineering. He has published over 300 technical papers and holds more than 50 US patents. Among his notable recognitions, he and his IMEC team received the 2014 Compound Semiconductor Industry Innovation award for their IIIV FinFET work. Aaron returned to Singapore in May 2016 to receive the National Research Foundation (Singapore)’s Returning Singapore Scientist Award and started his career in academia.
GaN Device Reliability Year-in-Review
The past few years have been exciting and extremely productive for the GaN community, and the research in the field of GaN-power devices has shown impressive advancements. In lateral GaN HEMTs, a two-dimensional electron gas (2DEG) is formed at the interface between GaN and AlGaN; the high mobility of the 2DEG (in excess of 2000 cm2/Vs) results in current densities around 1 A/mm, and in a very low on resistance (25 mΩ for a 650 V/60 A device). This implies a significant reduction in the resistive and switching losses, compared to silicon devices, and this has a positive impact on the efficiency of GaN-based power converters (kW-range power converters with efficiency higher than 99% have already been demonstrated, based on GaN HEMTs).
A relevant aspect that is currently under study is the reliability of GaN-based transistors. In fact, during operation in high-voltage power converters, the HEMTs may be subject to extreme field and current levels that may favor device degradation. In real-life applications, several potentially harmful conditions may be reached, favoring the exposure to off-state bias, semi-on stress conditions, hard switching, and high gate bias.
This presentation reviews the most recent results published in the field of GaN-based power transistors. After a brief introduction, we discuss the latest technology developments that have an impact on device reliability. Then, we summarize the most important papers on degradation and reliability published over the past year, with focus on the most relevant stress regimes (off-state, hard switching, positive gate bias, high temperature, etc.).
Matteo Meneghini received his PhD in Electronic and Telecommunication Engineering (University of Padova), working on the optimization of GaN-based LED and laser structures. He is now assistant professor at the Department of Information Engineering at the University of Padova. His main interest is the characterization, reliability and simulation of compound semiconductor devices (LEDs, Laser diodes, HEMTs). Within these activities, he has published more than 300 journal and conference proceedings papers. During his activity, he has cooperated and/or co-published with a number of semiconductor companies and research centers including:
-Panasonic Corporation (Japan)
-Universal Display Corporation (USA).
-NXP (The Netherlands)
-ON Semiconductors (Belgium/USA)
-Sensor Electronic Technologies (USA)
-Fraunhofer IAF (Germany)
-University of Cambridge (UK)
-Universiy of California at Santa Barbara (USA)
-University of Wien (Austria)
Memory Technology Reliability Year-in-Review
As they continue to pursue higher performance and densities at lower cost, semiconductor memory technologies have introduced novel materials and integration schemes from the cell to the packaging level. Understanding the reliability failure modes associated with these materials and processes is critical to providing a robust memory component. This presentation will review the major technology directions taking place in the areas of DRAM, NAND, and emerging memories. It will then review recent publications that identify the reliability concerns posed by these directions, with an emphasis on those that attempt to discern the underlying physics.
Bob Gleixner received his Ph.D. degree in materials science from Stanford University in 1998. He then joined Intel and for the next ten years worked on reliability characterization of microprocessor, microdisplay, and non-volatile memory technologies and products. Starting in 2004 Bob’s work focused on developing and productizing advanced Phase Change Memory technologies, first at Intel and later with Numonyx. He joined Micron in 2010 as part of the Numonyx acquisition, where he is now a Distinguished Member of the Technology Staff (DMTS). While at Micron he’s managed teams of silicon technology and product development engineers, with his main focus on the reliability of novel non-volatile memory technologies. He has published 13 technical papers and received 5 US patents.