2017 IRPS Workshops
The Tuesday evening workshops enhanced the symposium by providing the attendees an opportunity to meet in informal groups to discuss key reliability physics topics with the guidance of experienced moderators. Over 200 participants enjoyed the networking opportunities to meet with colleagues from around the world interested in common issues and joined in lively discussions of one or more of the six topic areas listed below. Summaries of each of the workshops can be found by clicking on the links in the table.
|COTS/System||Handshaking Between System Users and COTS Vendors||COTS Summary||Shijie Wen (Cisco)
Ken Label (NASA)
Ken Wu (TSMC)
Bharat Bhuva (Vanderbilt)
|Memory/Product||Solid State Drive (SSD) Reliability: From Flash Cells to Systems||Memory/Product Summary||Chandra Mouli (Micron)
Xiaoyu Yang (Sandisk)
Shosuke Fuji (Toshiba)
|MOL||MOL Dielectric TDDB Models||MOL Summary||Adrian Chasin (IMEC)
Tian Shen (GLOBALFOUNDRIES)
Shou Chung Lee (TSMC)
|Wide Bandgap||GaN Power Device Reliability Standardization||Wide Bandgap Summary||Matteo Meneghini (Padova)
Tim McDonald (Infineon)
|Transistor||Self Heating Effects on HCI and BTI: How worried should we be about it and what should we do about it?||Transistor Summary||Ashraf Alam (Purdue)
Andreas Kerber (GLOBALFOUNDRIES)
Chetan Prasad (Intel)
|Extrinsic||Juggling Knowledge Based and Standards Based Qualifications||Extrinsic Summary||Bob Knoell (NXP)
Jeffrey Hicks (Intel)
COTS/System: Handshaking between systems users and COTS vendors
This workshop will discuss the different views of reliability challenges of components from the silicon technology, to design, to application requirement, and the importance of early and close hand-shaking or collaboration from end to end in the chain to address the challenges.
ShiJie Wen has been with Cisco for the past 14 years in the department of quality and technology. He plays the active role in silicon technology, semiconductor component and system reliability, resilience, RAS in design and field.
Kenneth A. LaBel received his BES in EECS with a minor in Mathematical Sciences from The Johns Hopkins University in 1983. Since graduation, he has worked at NASA Goddard Space Flight Center (GSFC). His career at NASA has included development of:
Hardware/software for ground systems, Advanced technology, Flight hardware, Systems engineering, and, Radiation hardness assurance/research for >50 NASA projects.
He is currently co-manager of the NASA Electronic Parts and Packaging (NEPP) Program as well as senior staff engineer for the Radiation Effects and Analysis Group (REAG) at NASA GSFC. He has won multiple awards at NASA including the prestigious National Resource Award. Mr. LaBel has published over 100 papers as author/co-author, has taught multiple short courses at IEEE Nuclear and Space Radiation Effects Conference (NSREC), Hardened Electronics and Radiation.
Dr. Ken Wu has been with TSMC for 14 years, he is Sr. Director of Technology Quality & Reliability. Prior to join TSMC he had worked at Intel for 20 years in technology reliability area. Currently he is in charge TSMC advanced technology reliability characterization and qualification, covering manufacturing quality, component reliability, board-level and system-level reliability with closely engaging with customers.
Bharat Bhuva is a professor in Electrical Engineering and Computer Science department at Vanderbilt University. His main area of research is microelectronics reliability. His research group has evaluated soft-error vulnerability of each technology node since 180-nm node.
Memory/Product: Solid State Drive (SSD) Reliability from Flash Cells to Systems
Solid State Drive (SSD) is basically a storage device composed of NAND flash memory. However, its reliability is determined not only by memory cell reliability but also by controller technology such as ECC, wear leveling technique. In addition, users’ requirements for SSD reliability can be dependent on their use cases. Discussions including system and device engineers as well as users are thus indispensable for understanding and optimizing SSD reliability.
Chandra Mouli is with Micron Technology Inc., Boise, ID, USA. He is currently Director of Device Technology with responsibilities in the area of advanced device characterization, reliability analysis, test structure design/layout, process & device modeling for all technologies under development in R&D. He received his undergraduate degree in Physics and MSEE from the Indian Institute of Science (IISc), Bangalore, India and Ph.D (EE) from the University of Texas at Austin. He was with Texas Instruments for couple of years before joining UT/Austin. His interests include semiconductor devices and process technology for advanced memory, opto-electronic devices, exploratory research in the area of new materials and device structures. He has more than hundred issued patents and several pending in various areas of semiconductor devices and process – in advanced memory, novel devices and image sensor technology. He has served in the technical committees for various conferences, including IEDM, IRPS and SISPAD. He has also served in the review committees for NSF and SRC. He is currently a member of the scientific advisory board in SRC’s focus center programs and is a member of the ITRS technical working group.
Dr. Xiaoyu Yang is Sr. Engineering Director at SanDisk, a Western Digital Company. She has over 20 years of Q&R experience at various semiconductor companies. She received her Ph. D in Material Science & Engineering Department from Stanford University, M.S. in Physics Department from UC Irvine, and B.S in Physics Department from Peking University. She currently is in charge of the memory Reliability and Qualification division. Her responsibilities include new technology development, customer engagement, and product qualification.
Shosuke Fujii is a research scientist at Toshiba Corporation. He received BS and MS degrees in materials science and engineering from Kyoto University, Japan, in 2005 and 2007 respectively. He joined Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation in 2007. From 2007 to 2009, he engaged in reliability physics of MONOS type non-volatile memories. From 2009, he has been engaged in the research of emerging memory cell technology such as OxRAM, CBRAM, and novel ferroelectric memory. He served as co-chair of memory reliability session in IEEE International Reliability Physics Symposium (IRPS) in 2014 and 2015. He also served as a tutorial lecturer in IRPS in 2016.
MOL: MOL Dielectric TDDB Models
FEOL and BEOL reliabilities are well recognized fields of research and are proven to be crucial for device/circuit qualification. More recently, due to increased gate-to-contact proximity for advanced nodes only the spacer sidewall material provides isolation. Moreover, a trend exists towards thinner spacers (<10nm) to maximize contact area. In this regard, MOL reliability became also a crucial reliability aspect that has to be secured to avoid device malfunctioning. The main objective of this workshop is to discuss the possible models to extrapolate the accelerated experimental data set to device working conditions, because of its unique feature that differs from both FEOL and BEOL cases. However, the discussion will be by no means limited to this topic and other subjects will also be covered such as device layout, characterization techniques, impact of variability and materials choice.
Adrian Chasin is a senior researcher at imec – Belgium. He received the PhD in Electrical Engineering from the University of Leuven (KU Leuven) in 2014. During this time he developed and modeled new electronic devices based on amorphous oxide-semiconductors for flexible and large-area circuits targeting RF and display applications. After working at NXP as a research scientist responsible for advanced CMOS technologies evaluation, he joined the imec reliability group in 2015. His main research interests are FEOL and MOL reliability for sub-14 CMOS technologies. He authored and co-authored more than 50 publications.
Tian Shen received his B.S in physics from University of Science and Technology of China, Heifei, China. and Ph.D. in physics from the Purdue University, West Lafayette, Indiana in 2009. In 2010 he became a guest researcher at National Institute of Standards and Technology, Gaithersburg, MD working on quantum transport on graphene nano devices. He joined GLOBALFOUNDRIES in 2012 working on semiconductor BEOL reliability issues including EM, SM and TDDB from 32 to 7nm technology nodes. He has numerous scientific publications in the area of semiconductor devices, materials, and physics.
Shou-Chung Lee received the B.S. (1994) in physics from National Sun Yet-Sen University, Kaohsiung, Taiwan and M. S. (1996) from Institute of Electro-Optical Engineering of National Chiao Tung University, Hsinchu, Taiwan. In 1998, he joined TSMC where he worked on Aluminum and Copper interconnect reliability. In 2011, he received Ph.D. degree in electronics engineering from National Chiao-Tung Univ., Hsinchu, Taiwan. He has served on the dielectric committee as a co-chair for 2015 International Reliability Physics Symposium (IRPS). His research interests include Cu interconnect reliability, BEOL and MOL dielectric reliability.
Wide Band Gap: GaN power devices reliability standardization
Over the last few years, GaN has emerged as an excellent material for the fabrication of high voltage/current transistors, that will rapidly find application in the next-generation power conversion systems. 650 V/60 A transistors are already commercially available, and 1200 V devices are under development. Several papers investigated the failure modes and mechanisms of GaN-based power HEMTs, providing pathways for the improvement of this technology. However, there is no standard for the qualification of the reliability, and several questions are still open: Is dynamic Ron still a problem? How to standardize the pulsed measurements? Which testing procedures must be used for reliability estimation/assessment? Are there specific degradation processes that are not present in silicon? This workshop will address these questions, by stimulating the discussion on the standardization of reliability procedures for the development of GaN-based power HEMTs.
Matteo Meneghini received his PhD in Electronic and Telecommunication Engineering (University of Padova), working on the optimization of GaN-based LED and laser structures. He is now assistant professor at the Department of Information Engineering at the University of Padova. His main interest is the characterization, reliability and simulation of compound semiconductor devices (LEDs, Laser diodes, HEMTs).
Tim McDonald is currently Senior Director, GaN Technology Development, worldwide Applications and Marketing for Infineon Technologies’ Gallium Nitride on Silicon power devices. He is responsible for defining applications and bringing to market Infineon’s GaN on Silicon-based power devices.
Previously, Tim was Vice President of device engineering and product development for International Rectifier’s GaNpowIR™ Technology Development team where he was responsible for successfully developing and marketing GaN on Silicon devices into consumer high volume applications. Before that he served as Vice President of IR’s iPOWIR™ Power Stage Business Unit where he was responsible for defining and developing integrated DC-DC power conversion solutions with benchmark efficiency and power density for application in netcom, servers, mobile computing and game stations.
Tim has over 30 years of diversified experience in power conversion/management holding positions in device engineering management, product and market development, product engineering, device characterization, test platform development and operations. Tim holds a Bachelor of Science degree in Physics from UCLA.
Transistor: Self-heating effects on HCI and BTI: How worried should we be and what should we do about it?
The issue of localized self-heating is relatively new to scaled CMOS devices, such as FinFETs, fabricated on bulk-Si substrates, but it has been known to affect the performance/reliability of partially and fully depleted SOI devices for many generations. Thus, self-heating corrections were frequently employed in the HCI assessment for SOI devices. Comprehending self-heating on HCI and BTI in scaled discrete devices and CMOS circuits relies on accurate thermal modeling for circuits operating at high frequencies. Such thermal modeling must not only account for the power dissipated and the thermal resistances, but also comprehend the open boundary conditions associated with mobile devices, such as tablets and cell phones. The intent of this workshop is to discuss the characterization and modeling approaches for localized self-heating in advanced technology nodes, and to highlight areas which need further attention.
Professor Ashraf Alam holds the Jai N. Gupta professorship at Purdue University, where his research focuses on the physics and technology of semiconductor devices. From 1995 to 2003, he was with Bell Laboratories, Murray Hill, NJ, as a Member of Technical Staff in the Silicon ULSI Research Department. Since joining Purdue in 2004, Dr. Alam has published over 250 papers and has presented many invited and contributed talks. He is a fellow of IEEE, APS, and AAAS. His awards include the 2006 IEEE Kiyo Tomiyasu Medal for contributions to device technology and 2015 SRC Technical Excellence Award for fundamental contributions to reliability physics. Prof. Alam enjoys teaching — more than 100,000 students worldwide have learned some aspect of semiconductor devices from his web-enabled courses.
Andreas Kerber was born in Schnann, Austria. He received his Diploma in physics from the University of Innsbruck, Austria, in 2001 and a PhD in electrical engineering from the TU-Darmstadt, Germany in 2004 (granted with honors). He worked as an intern at Bell Laboratories, Lucent Technologies, Murray Hill, NJ, USA (1999-2000), at IMEC in Leuven, Belgium (2001-03) as Infineon Technologies assignee to International SEMATECH, for the Reliability Methodology Department at Infineon Technologies in Munich, Germany (2004-06), for AMD in Yorktown Heights, NY (2006-09), and as a Prinicpal Member of Technical Staff for GLOBALFOUNDRIES in Malta, NY (since 2009). Much of his work centered around Front-End-Of-Line (FEOL) reliability research with focus on metal gate / high-k CMOS technologies. He has co-authored over 100 papers in Journals and Conferences.
Chetan Prasad received a Bachelor’s degree in telecommunications engineering from the University of Mumbai in 1997, and completed a Masters and PhD in electrical engineering from Arizona State University in 1999 and 2003 respectively. He joined the Technology Development Quality and Reliability (TD Q&R) organization at Intel Corporation in 2003 as a senior reliability engineer, working on transistor and dielectric reliability R&D across the 90nm through 14nm process technology nodes. From 2012-15, Chetan was the Q&R manager for Intel’s 14nm SoC technology, and he is currently the Q&R manager for Intel’s 7nm technology. He has authored/co-authored over 60 papers as invited, journal and conference publications and has awarded and pending US patents. His industry engagements include contributions to IRPS technical committees and tutorials, journal reviews and JEDEC standard definitions.
Extrinsic: Juggling Knowledge Based and Standards Based Qualifications
This compromise can also be between application-specific and stress-test based qualification methods or between physics-of-failure and right-censored testing. In one case, an application that fits, say, the 90th percentile of customer usage that utilizes one set of tests, conditions and durations versus one where the application determines a variable set of tests, conditions and durations. In the other case, a set of tests, conditions and durations that are based on the acceleration of known specific physical failure mechanisms versus a set of tests, conditions and durations based on a set of known stimuli such as temperature, humidity and mechanical stress experienced in the field. This workshop will discuss the advantages and limitations of each method to give the participants an idea of when to utilize each for their qualification program.
Bob Knoell has worked for NXP for 6 years as a customer quality manager and, now, as an industry standards and customer contract manager. Previously, he worked 19 years at Visteon, mostly as a specialist in semiconductor reliability and at AT&T Bell Labs for 10 years performing research as a member of technical staff. He is currently the chair of the Automotive Electronics Council (AEC), chair of JEDEC JC14.3 Reliability Qualification Methods, and a member of AIAG, SAE Reliability Committee, and USCAR. He holds a bachelors in Physics from SUNY Stony Brook, a masters in materials engineering from Stevens Institute of Technology and a masters in engineering management from Wayne State University. His hobbies include playing baseball, golf and track. His interests include history, politics, astronomy and theoretical physics. He is married with two daughters.