Transistor Reliability

Transistor Reliability

XT-1 Alteration of Oxide-Trap Switching Activity at Operating Condition By Voltage-Accelerated Stressing

Z.Y.Tung, D.S. Ang, Nanyang Technological University

It is found that voltage-accelerated stressing can change the switching activity of a time-zero oxide defect measured under operating condition. The defect can be rendered either less active or more active by the applied stress, implying a possible modification of its atomic structure. With the impact of oxide trapping on MOSFET channel conduction becoming increasingly important as device dimension decreases, the observed stress-induced alteration of trap-switching behavior under operating condition should be a consideration in the reliability assessment of small-area devices.

XT-2 Nano-Scale Evidence for the Superior Reliability of SiGe High-k pMOSFETs

M. Waltl, A. Grill, G. Rzepa, W. Goes, J. Franco*, B. Kaczer*, J. Mitard*, T. Grasser, TU Wien, *imec

It has recently been demonstrated that the susceptibility of conventional Si channel pMOSFETs to the negative bias temperature instability (NBTI) is a serious threat to further scaling. One possible solution to this problem is the use of SiGe quantum-well devices, which not only offer high mobilities but also superior NBTI reliability. It has been speculated that the latter is due to the band offset of the SiGe channel with respect to Si, which increases the energetic separation between the defect bands in the high-k gate stack and the channel. We investigate this claim by comparing single-defects in nano-scale devices to the behavior of the large number of defects visible in large-area devices. Using detailed TCAD simulations we determine the energetic and spatial locations of the traps in the gate stack and confirm that the previously developed picture correctly explains the significant reliability benefits of SiGe channel devices.

XT-3 Negative Bias Temperature Instability Lifetime Prediction: Considering Frequency, Voltage and Activation Energy via Novel Methodology of MSM-SFMF

C.H. Chiang, N. Ke, S. N. Kuo, C. J. Wang, K. C. Su, United Microelectronics Corporation

The reliability of pMOSFETs is limited by NBTI. Recent NBTI studies for aggressive scaling CMOS technology found the recoverable component. According to the present observation, the recoverable component is contributed by hole trapping while the permanent component is explained by the creation of interface. It implies that NBTI results from two tightly coupled mechanisms. This paper discusses a new measuring skill that helps us to realize characteristic of traps via frequency, voltage and temperature [4]. After considering activation energy (Ea), traps can be divided into three types. It includes simple concept of Reaction-Diffusion (RD) and two-stage models, and doesn’t need complicated mathematics operations. Consequently, it benefits the study of transistor NBTI behavior.

XT-4 Device-Level Jitter as a Probe of Ultrafast Traps in High-k MOSFETs

D. Veksler, J. Campbell, J. Zhong*, H. Zhu*, C. Zhao*, K. Cheung, National Institute of Standards and Technology, *Chinese Academy of Sciences, *IMECAS

We developed the methodology to quantify ultra-fast interface traps using jitter measurements as a probe. This methodology was applied to study the effect of PBTI stress in high-k/Si MOSFET on density of fast interface traps (500ps to 5ns timescale). It was shown that increase of jitter of 2Gbt/s signal caused by stress is solely related to the degradation of a FET threshold voltage, while density of fast interface traps is not affected by PBTI stress. The developed methodology can be used for evaluation of the interface quality and quantification of fast interface traps in MOSFET and HEMT devices, built using different technologies and material systems. It can be used to study interface degradation induced by different type of stresses, including electric, thermal, and radiation effects.

XT-5 Spatio-Temporal Mapping of Device Temperature due to Self-Heating in Sub-22nm Transistors

M.A. Wahab, S. Shin, M.A. Alam, Purdue University

With the increase of transistor density and adoption of novel geometries, such as, FinFET, ETSOI, and gate-all-around (GAA) transistors, self-heating has emerged as a persistent concern for modern ICs. Various reliability issues, such as, NBTI, HCI, PBTI, and TDDB depend sensitively on channel temperature, 〖ΔT〗_C (x,y,z;t), due to self-heating. An accurate spatio-temporal map of channel temperature is essential for Fin-resolved reliability/lifetime of sub-22 nm technology nodes. In this paper, we demonstrate that (i) none of the existing techniques, in isolation, can map the Fin-resolved channel temperature of modern transistors, and (ii) only a collection of orthogonal techniques (multiprobe approach) or novel test structures (material approach), integrated/interpreted through self-consistent electro-thermal simulation, can map the temperature in sufficient detail necessary for reliability prediction.

XT-6 Surface-Potential-Based Compact Modeling of BTI

I.S. Esqueda, H. Barnaby*, University of Southern California, *Arizona State University

Characterization and modeling of bias temperature instability (BTI) is conventionally based on time-dependent shifts in threshold voltage (Vth) resulting from stress and relaxation conditions. Contributions of oxide near-interfacial (i.e., border) and interface traps are not independently captured in these conventional methods. By considering the effects of charge trapping dynamics on MOSFET operation, we present new techniques for characterizing and modeling the contributions of oxide and interface traps. Characterization is based on the rapid response of interface traps to high-frequency measurements of inverse subthreshold slope (S), for which slower oxide traps do not contribute, as their occupancy does not change at high frequencies. The modeling approach uses calculations of surface potential (ψs) to describe the distinct contributions of oxide and interface traps on BTI. Combined with capture/emission time maps, this approach describes BTI induced ΔS, and ΔVth stress/recovery characteristics.

XT-7 Width and Layout Dependence of HC and PBTI Induced Degradation in HKMG nMOS Transistors

N. Mahapatra*, P. Duhan, V. Rao, Indian Institute of Technology Bombay, *Indian Institute of Technology Gandhinagar

In this abstract, we have studied the width dependence of HC and PBTI induced degradation in HKMG nMOS transistors. It is clearly shown that the oxygen vacancies play a major role in the long term reliability of the HKMG nMOS transistors and this could be improved by dividing the active into multiple active fingers and by increasing the active-to-active spacing.

XT-8 Characterization and Modeling of NBTI Permanent and Recoverable Components Variability

D. Nouguier, X. Federspiel, G. Ghibaudo*, M. Rafik, D. Roy, STMicroelectronics, *University of Grenoble Alpes

In this paper we use a statistical analysis of NBTI recoverable and recoverable component measured on Pfet device issued from ST Microelectronics 28nm FDSOI technology. From measurement of NBTI degradation and recovery measured at μs time scale, resulting from AC and DC stress, we performed statistical analysis of the permanent and recoverable components and analyzed it separately. Accordingly, we proposed a Dual Defect Centric Model (DDCM) to account for differences of these two components.

XT-9 Temperature Sense Effect in HCI Self-heating de convolution – Application to 28nm FDSOI

X. Federspiel, G. Torrente, W. Arfaoui, V. Huard, F. Cacho, STMicroelectronics

Hot carrier injection (HCI) remained a major reliability concern for advanced CMOS nodes due to lateral field increase with device scaling but also due to increase of power dissipation [1,2,3,4]. HCI was reported as a wear-out mechanism that induces interface traps and oxide traps which cause in turn MOS device parameter drift. Parameter drift models were published to take into account lateral field, impact ionization, carrier energy distribution as well as local channel temperature. Recently, the need to deconvolute self-heating from HCI apparent voltage acceleration was pointed out to obtain accurate reliability modeling [5,6,7]. We will show here, that calculating temperature activation as if only depicting defect generation activation is an incomplete description of temperature dependency and that parameter drift temperature sensitivity factor must also be taken into account to correctly model HCI out. In the following, sense effect will refer to sensitivity of MOS parameter drift to temperature for a constant number of defect.

XT-10 Comparative Experimental Analysis of Time-dependent Variability using a Transistor Test Array

M. Simic, A. Subirats*, P. Weckx*, B. Kaczer*, J. Franco*, P. Roussel*, D. Linten*, A. Thean*, G. Groeseneken, G. Gielen, KU Leuven, *IMEC

As the transistors dimension reach the deca-nanometer scales, time-zero and time-dependent variability, which includes Random Telegraph Noise (RTN) and Bias Temperature Instability (BTI), become a great concern for IC design. Accurate statistical models describing these two variability sources are necessary in order to design reliable circuits and systems. This paper gives insights in the geometry scaling of these variabilities and studies time-dependent variability through three different measurement techniques: the 2-point Measure-Stress-Measure, the Time Dependent Defect Spectroscopy, and the precise IdVg. Advantages and downsides of each technique are discussed.