IRPS

Soft Errors

Soft Errors

SE-1 Alpha-Particle and Neutron-Induced Single-Event Transient Measurements in Subthreshold Circuits

M. Gadlage, J. Albhin*, P. Gadfort**, S. Stansberry***, A. Roach, A. Duncan, M. Kay, NSWC Crane, *MDA, **Army Reseach Lab, ***USC-ISI

Experimental data from alpha particle testing are dis-cussed and analyzed from a sub-threshold voltage SET characterization circuit. Using a Schmitt trigger inverter target chain fabricated in a 28-nm bulk CMOS process, SET pulse widths are captured from an operating voltage down to 0.32 V. These results show that alpha particles can induce SET pulse widths that range up to hundreds of nanoseconds when operating at voltages well below the nominal voltage. Additionally, the alpha particle results show that sub-Vt circuits are significantly more susceptible, as compared to circuits operating at nominal voltages, to low-energy particles inducing SETs that have a high probability of being latched as errors in a combinatorial logic design.

SE-2 Error Characterization and Mitigation for 16nm MLC NAND Flash Memory under Total Ionizing Dose Effect

Y. Li, D. Sheldon*, A. Ramos, J. Bruck, California Institute of Technology, *NASA Jet Propulsion Laboratory

This paper investigates the system-level reliability that 16nm MLC NAND flash can offer to SSDs under total ionizing effect for storage in space. Measurements show that blocks that carried less than 3k program/erase cycles (PECs) only survived up to 10k rad total doses under the protection of standard ECCs. We characterize errors at the levels of threshold voltage Vt, cell logical state, and binary bit, respectively, and study error mitigation schemes for reliability enhancement. We adopt a novel data representation where data are read using the relative order of cell voltages.
Experimental results show that the new representation reduced bit errors by 60% on average. We propose a new memory scrubbing (MS) scheme that refreshes cells without block erasure and operates under lower voltage. Measurements show that flash blocks survived up to 8k PECs and 57k rad total doses using the new scrubbing scheme. Both schemes were implemented as parts of a flash controller, and significantly outperform existing methods in various aspects.

SE-3 Investigating the Single-Event-Transient Sensitivity of 65 nm Clock Trees with Heavy Ion Irradiation and Monte-Carlo Simulation

V. Malherbe, G. Gasiot, S. Clerc, F. Abouzeid, J.-L. Autran*, P. Roche, STMicroelectronics, *Aix-Marseille Université

We present a study of single-event transients in clock tree structures in 65 nm bulk silicon technology. Shift registers are irradiated with heavy ions over a large range of linear energy transfers representative of both terrestrial and space environments. By attributing large error clusters in the flip-flop shifters to clock tree events, we derive experimental cross sections for the clock tree cells. Monte-Carlo irradiation simulations performed on the same structures are in good agreement with these data, allowing to assess the radiation robustness of other clock-tree configurations.

SE-4 Exploiting Low Power Circuit Topologies for Soft Error Mitigation

N. Mahatme, S. Jagannathan, N. Gaspard,III*, B. Bhuva**, S. Wen***, R. Wong***, I. Chatterjee^, T. Assis**, NXP Semiconductor, *Altera Corporation, **Vanderbilt University, ***Cisco, ^University of Bristol

Alpha particle experimental results for arithmetic circuits implemented using transmission gate logic in 20-nm bulk technology node are shown to have 35% lower soft error rate as well as 30% lower power consumption compared to standard CMOS circuits. Analytical models confirm the experimental trends and help optimize and predict the power-SER trade-off.

SE-5 Estimation of Single-Event Transient Pulse Characteristics for Predictive Analysis

T. Assis, J. Kauppila, B. Bhuva, R. Schrimpf, L. Massengill, R. Wong*, S. Wen*, Vanderbilt University, *Cisco

Estimate the Single Event Transient (SET) pulse width of standard cells is challenge task requiring hundreds of spice simulations for the library characterization. In this work analytical models are used to estimate the SET pulse width for multiple standard cells considering both different hit node locations and charge sharing. By using the Ambipolar-Diffusion-Cutoff (ADC) model extension this methodology is also able to properly model the SET Pulse Quenching effect. The model requires a simple characterization step performed only once for 3 simple circuits. Comparison with electrical simulations (SPICE) for 4 technologies shows great model accuracy. Heavy ion experiments in a 65nm bulk technology Test Chip also show good accuracy. The simple model formulation and low computational requirements make this methodology ideal to be used by Electronic Design Automation (EDA) tools.

SE-6 Predicting the Vulnerability of Memories to Muon-Induced SEUs with Low-Energy Proton Tests Informed by Monte-Carlo Simulations

J. Trippe, R. Reed, B. Narasimham*, B. Sierawski, R. Weller, R. Austin, L. Massengill, B. Bhuva, K. Warren, Vanderbilt University, *Broadcom Corporation

Low-energy terrestrial muons have been shown to induce single-event upsets (SEUs) in complementary metal-oxide semiconductor (CMOS) static random access memories (SRAM). Only a handful of facilities produce surface muon beams, and these facilities have limited access to muon beamtime. As a result, it is difficult to carry out experiments to evaluate and/or characterize vulnerability to muons. To address the lack of muon beam availability, this work presents a method for determining a design’s vulnerability to muon-induced upsets by performing tests at a readily available, low energy proton facility. It is shown that low-energy protons have similar characteristics as muons for soft error effects. This will allow test engineers to use proton test results to determine if a device is vulnerable to muon induced upsets.