Session 7C – Product IC Reliability
Session 7C – Product IC Reliability
Session Co-Chairs: Jerry Lee, Cisco, Brian Pedersen, Intel
1:25 p.m. – Session Introduction
7C.1 BTI Induced Dispersion: Challenges and Opportunities for SRAM Bit Cell Optimization
F. Cacho, A. Cros, X. Federspiel,V. Huard, C.Roma*, STMicroelectronics, *MunEDA
A One major CMOS reliability concern for advanced nodes is the Bias Temperature Instability (BTI) mechanism. In addition to the native local process dispersion, the BTI induced dispersion is a field under intensive research. Important works [1, 2] focus on the distri-bution tail of the Vth shift and efforts are deployed to high-sigma accurate modeling (defect centric, skellam). In most applications influ-enced by devices matching (ADC, SRAM…), it is important to understand how the initial Vth distribution evolves in time. In this paper some key results of spread induced by BTI are reviewed for 14FDSOI and 28FDSOI from STMicroelectronics. Analysis between initial Vth and aged Vth correlation is presented. Then, measurement of fresh and post HTOL memory VDDmin is presented for different conditions of temperature and process centering. Finally, an innovative algorithm of yield optimization is presented. It enables to optimize the centering and yield (through devices sizing or process centering) including ageing, under constraint of foot print.
7C.2 Aging-aware Adaptive Voltage Scaling of Product Blocks in 28nm Nodes
V. Huard, F. Cacho, A. Benhassain, C. Parthasarathy, STMicroelectronics
In this work, we have demonstrated the fundamental elements towards an Aging-aware AVS scheme of digital circuits. First, we have demonstrated that a new generation of aging monitors, named IS2M, is needed to accurately track the aging-induced delay degrada-tions. In a second time, Aging-aware AVS voltage regulation has been experimentally assessed on two different testcases. Overall, 6-7% power reduction has been demonstrated at the beginning of the life and 2-3% at the end-of-life situation. Even though the regulated voltage increases, most of the power reduction is maintained over the whole mission profile. This study offers new perspectives towards product hardening and qualification with respect to an adaptive approach to real user-based workloads.
7C.3 Scenario-based Set-level HTOL Test (ASH III) for Product Quality and Reliability Qualifications on High-Speed Aps
J. Park, J. Kim, M. Choe, H. Shim, W. Kim, S. Park, S. Shin, Y. Kim, J. Jeong, H. Shin, H. Lee, S. Pae, Samsung Electronics Co., Ltd.
In a streak of the set level stress test for high speed mobile application processor (AP) reliability , At-Speed HTOL (ASH) incorporated by user conditions was employed to realistically project the field failure rate of product. Using the worst case scenario test with different frequency and operation duty, the failure modes veiled behind the conventional HTOL can be surfaced and then reconciled, which is further evolved as a failure screening technique during volume production. In addition, the simulation methodology to determine product Vmin-GB in pre-silicon phase is also developed and compared to the Product Vmin-GB results. The results of ASH with scenario test can extend our understanding of an effective methodology to ensure robust design from design for test (DFT) and to achieve decent field failure target.
7C.4 Reliability Characterizations of Display Driver IC on High-k / Metal-Gate Technology
D. Kim, J. Kim, K. Bae, H. Kim, L. Hwang, S. Shin, H.-N. Park, I.-T. Ku, S. Pae, J. Park, H. Lee, Samsung Electronics Co., Ltd.
Display Driver IC is used to operate the display panel of mobile devices, such as handheld smartphones and tablets. Recently, High-k (HK)/ metal-gate (MG) process was used to fabricate DDI products for low power applications. We’ll discuss the abnormal leakage increase observed during HTOL and explain the physical mechanism and process fixes implemented. As result, final DDI product showed an excellent reliability results through 1500hrs of HTOL exceeding product EOL.