Session 6C – Memory
Session 6C – Memory
Session Co-Chairs: Robin Degraeve, imec, Christian Monzio Compagnoni, Polytechnico di Milano
8:30 a.m. – Session Introduction
6C.1 Quantitative Model for Post-program Instabilities in Filamentary RRAM
R. Degraeve, A. Fantini, G. Gorine*, P. Roussel, S. Clima, M. Chen, B. Govoreanu, L. Goux, D. Linten, M. Jurczak, A. Thean, imec, *University of Pavia
Filamentary vacancy-based RRAM devices show post-program instability, making Incremental Step Pulse Program (ISPP) algorithms highly ineffective. This is because after the verify step, both the Low and High Resistive State distributions always evolve towards a wider natural distribution. In this paper, we describe this instability in the context of the hourglass model. Both HRS and LRS distributions have two variability sources: (i) number variations of the amount of vacancies in the filament constriction and (ii) constriction shape variations. The shape variations show a log(time)-dependent relaxation behavior after each programming pulse, resulting in program instability. This is mathematically described as an auto-correlated step process of the shape parameters in the QPC conduction model.
6C.2 Extensive Reliability Investigation of a-VMCO Nonfilamentary RRAM: Relaxation, Retention and Key Differences to Filamentary Switching
S. Subhechha*, B. Govoreanu, Y. Chen, S. Clima*, K. De Meyer*, J. Van Houdt*, M. Jurczak, imec, *also with KU Leuven
Vacancy Modulating Conductive Oxide resistive switching devices use electrical modulation of the defect profile to vary the conductance of tunneling barrier, thereby operating with self-rectification and self-compliance. They have been demonstrated to show low switching current with area scalability, indicating non-filamentary switching, and thus making them very promising candidates for high density memory applications. In this work, we report on room temperature and higher temperature retention, with extensive study on parametric dependence – the impact of electrical, material, and process parameters. In addition, we highlight differences with respect to filamentary switching, and suggest directions for improvement.
6C.3 A Step Ahead Toward a New Microscopic Picture for Charge Trapping/detrapping in Flash Memories
D. Resnati, C. M. Compagnoni, G. Paolucci*, C. Miccoli*, J. Barber*, M. Bertuccio*, S. Beltrami*, A. Lacaita, A. Spinelli, A. Visconti*, Politecnico di Milano, *Micron Technology Inc.
Scaling of integrated MOS technologies into the deca-nanomenter regime represented a historic moment for the reliability community, opening the possibility of observing long-debated issues from the new perspective of charge and matter granularity. In the last years, this resulted in a fundamental revision of the physical understanding of Negative Bias Temperature Instability (NBTI) and Random Telegraph Noise (RTN). Following this path, in this work we present clear experimental results leading to a new microscopic picture for charge trapping/detrapping in Flash memories, representing one of the most relevant constraints to the operation of state-of-the-art arrays. The gathered experimental evidence is implemented in a statistical model able to reproduce the charge trapping/detrapping dynamics along the memory array lifetime.
6C.4 Channel and Near Channel Defects Characterization in Vertical InxGa1-xAs High Mobility Channels for Future 3D NAND Memory
A. Subirats, E. Capogreco, R. Degraeve, A. Arreghini, D. Linten, G.Van den bosch, J. Van Houdt, A. Furnemont, imec
In this paper, we present a first characterization of the charge trapping in vertical 3D SONOS with InxGa1-xAs channel using IV hysteresis and RTN measurements. We show that III-V devices have a high density of border traps leading to an important variability its electrical parameters. Finally, individual trap analysis show that the III-V devices also possess traps in the channel region and their behavior is similar to the one measured in silicon technology.
6C.5 Data-Retention Time Prediction of Long-term Archive SSD with Flexible-nLC NAND Flash
T. Takahashi, S. Yamazaki, K. Takeuchi, Chuo University
This paper proposes a new method to predict the data-retention time of long-term archive SSD with flexible-nLC NAND flash. This paper first reports that the conventional prediction overestimates the data lifetime. Then, a more
precise prediction is proposed. By using the proposal, the most reliable and lowest cost memory architecture is determined. As a result, over 100-year data-retention is achieved, which is 25-times longer than the conventional TLC NAND flash memory.
6C.6 Data Archiving in 1x-nm NAND Flash Memories: Enabling Long-Term Storage using Rank Modulation and Scrubbing
Y. Li, E. En Gad, A. A. Jiang*, J. Bruck, California Institute of Technology, *Texas A&M University
Archival data once written are rarely accessed by user, and need to be reliably retained for long periods of time (e.g., 10 ∼ 100 years). The challenge of using inexpensive NAND flash to archive cold data was posed recently for saving data center costs. However, high density flash is vulnerable to charge leakage over time, and a recent study shows that flash will be cost-competitive to HD in archival systems if longer retention periods (RPs) can be achieved. This paper investigates the system-level reliability of archival storage that uses the cheapest 1x-nm NAND flash. We analyze retention error behavior, and show that 1x-nm MLC and TLC flash do not immediately qualify for archival storage. We then implement the rank modulation (RM) scheme and memory scrubbing (MS) in flash controller for RP enhancement. RM takes advantage of the asymmetric threshold voltage drift for higher reliability, and provides a new data representation using the relative order of cell voltages. Measurements show that the new representation reduces raw bit error rate (RBER) by 45% on average, and using RM and MS together provides up to 58, 128 and 196 years of RPs at ECC code rates 0.84, 0.82 and 0.80, which outperforms conventional methods by 480%, 49% and 18%, respectively.