Session 6B – 3D Assembly
Session 6B – 3D Assembly
Session Co-Chairs: Chandrasekara Kothandaraman, IBM, Kangwook Lee, Tohoku University
8:30 a.m. – Session Introduction
6B.1 Impact of Local Stress in 3D Stacking Process on Memory Retention Characteristics in Thinned DRAM Chip
S. Tanikawa, H. Kino, T. Fukushima, K. Lee, M. Koyanagi, T. Tanaka, Tohoku University
The influence of local stress on memory retention characteristics has been characterized. The retention time of memory cells in the DRAM chip with 200-μm thick was largely changed after under-fill and curing of epoxy layer especially near and between Cu/Sn bumps. Meanwhile, after thinned down to 40-μm thick, the retention time of memory cell was not significantly changed on the whole even regardless of the positions of Cu/Sn bump. We assumed that the local stress generated by under-fill of epoxy adhesive gave larger effects on the memory retention characteristics than the stress generated by Si thinning until 40-μm-thick.
6B.2 Impact of Wafer Thinning on Front-end Reliability for 3D Integration
A. Chasin, M. Scholz, W. Guo, J. Franco, G. Potoms, A. Jourdain, D. Linten, G. Van der Plas, P. Absil, E. Beyne, Imec
The impact of wafer thinning down to 5 μm Si thickness is assessed in advanced planar and finFET CMOS technologies. Both Bias Temperature Instability (BTI) and Electrostatic Discharge (ESD) reliability are not impacted by the reduction of the substrate thickness.
6B.3 Triangular Voltage Sweep (TVS) Characterisation for Through-Silicon-Via (TSV) Reliability
C. Kothandaraman, S. Cohen, IBM Research
We demonstrate the use of TVS for reliability characterization of TSV. TVS complements conventional methods of dielectric reliability characterization such as VBD and TDDB. TVS is used to study copper diffusion out of the TSV and the impact of TSV process on neighboring devices.
6B.4 The Projection of the Incidence of Dielectric Cracking During Chip Joining with Lead Free Solder Bumps
T. Shaw, E. Misra*, D. Questad*, X. H. Liu, G. Bonilla, T. Wassick*, H. Shobha**, K. Smith*, G. Osborne*, D. Koiussis*, J. Wright*, R. Bisson**, I. Paquin***, M. Lamorey*, S. Bouchard***, S. Tetreault***, D. Stone*, C. Muzzy*, B. Sundolf*, T. Daubenspeck*, IBM T.J. Watson Research Center, *IBM Microelectronics, **IBM at Albany Nano-Technology Center, ***IBM Canada Ltd 23
This study examines different approaches to determining the chip failure rate that occurs due to dielectric cracking under C4 sites during chip joining. We show that testing of the strength of individual C4s by a single bump shear technique gives a strength distribution that is well described by a Weibull distribution with a Weibull modulus that lies in the range 10-20. Simulations of the spatial distribution of failing C4s during a chip joining test using this distribution, however, are found to be inconsistent with those observed experimentally. From this observation we conclude that the observed fails arise from a defect population that is not well characterized by single bump shear tests. We propose an alternative to SBS testing in which we directly count the number of fails that occur at a given stress level by comparing the location of the fails observed in multiple sonoscan images of chips to the C4 stress map calculated from a finite element model. An example is presented where the strength distribution of the defect tail is characterized from the analysis of C4 fails induced by an accelerated chip joining test. From this distribution we show how it is possible to project chip failure rates that arise from a manufacturing chip joining process.
6B.5 Key Metrics for the Electromigration Performance for Solder and Copper-based Package Interconnects,
C. Hau-Riege, Y.-W. Yau, K. Caffey, Qualcomm Technologies, Inc.
This paper presents EM results over a wide spectrum of far backend interconnects, including microbump, thermal compression flip chip bump, copper pillar, lead free bump and solder ball, in order to identify the unifying themes for electromigration failure modes and performance enhancement. In all cases, CuSn is formed in the solder region. For
structures with high solder-to-Cu ratios (e.g., solder balls, lead-free bumps, or Cu pillars on narrow traces), failure occurred along the interface of the CuSn and solder on the cathode-side. For structures with low solder-to-Cu ratios (e.g., Cu pillars and TCFC bumps on wide traces or pad, and microbump), solder totally transforms into CuSn during EM test. In this steady-state (or near steady-state) configuration, no further evolution occurs; that is, there are no significant EM voids and the resistance is relatively stable. Based on our studies, the transition between “high” and “low” regimes occurs in the range of solder-to-Cu ratios of 2.5 to 3.
6B.6 The State of Pb-free Solder – A Joint Reliability Overview (Late News)
V. Vasudevan, T. Schulz, M. Pei, F. Toth, A.E. Lucero, B. Zhou, S. Mukherjee, Intel Corporation
Over the past decade the electronics components industry successfully transitioned from the use of leaded solder to lead-free (Pb-free) solders in response to growing environmental health concerns related to heavy metals and other substances. Pbfree components in general are in compliance to meet the European restriction of hazardous substances (RoHS) directives. During the transition period to Pb-free surface mount, numerous issues were raised about the selected alloys, the board assembly process and reliability. Early Pb-free reliability concerns were due to incomplete analytical understanding of the Tin-Silver-Copper solder creep-fatigue behavior, difficulty in computing the magnitude of ball grid array (BGA) relative displacements or strains and lack of product field history. Since then the failure mechanisms were characterized and many models are in common use for reliability estimation and design. This manuscript revisits the initial concerns, reliability model use evolution and summarizes the current understanding that has resulted in a decade of reliable field operation for the Pb-free SAC solders selected.