Session 6A – ESD and Latch-up

Session 6A – ESD and Latch-up

Session Co-Chairs: Dimitri Linten, imec, Teruo Suzuki, Socionext
Section D

8:30 a.m. – Session Introduction

8:35 a.m.

6A.1 FinFET SCR Structure Optimization for High-Speed Serial Links ESD Protection

L.-W. Chu, Y.-F. Chang, Y.-T. Su, K.-J. Chen, M.-H. Song, J.-W. Lee, TSMC

We proposed here is a low capacitance SCR optimized for turn-on speed and parasitic capacitance in FinFET CMOS process. Experimental results indicate that our proposed optimal FinFET SCR structure delivers the best known results among the literatures (140mA/fF). By adopting the structure, a high-speed transceiver for operating at multi Gb/s can be easily realized.

9:00 a.m.

6A.2 Interposer FPGA with Self-protecting ESD Design for Inter-die Interfaces and its CDM Specification

J. Karp, M. Hart, M. Fakhruddin, V. Kireev, P. Tan, D. Tsaggaris, M. Rawatt, Xilinx, Inc.

ESD protection of inter-die interfaces is discussed for the second generation of 20nm interposer FPGA, where ESD elements are optimized to reduce die cost. Self-capacitance is used to estimate the CDM exposure of bare die in the interposer assembly flow. A 50V CDM passing voltage of inter-die interfaces is related to the 200V CDM S20.20-2014 specification.

9:25 a.m.

6A.3 Investigation of Reverse Recovery Effects on the SOA of Integrated High Frequency Power Transistors

K. Rajagopal, A. Concannon, P. Hower, F. Farbiz, A. Salman, J. Arch, P. Elo, Texas Instruments

Switching frequency and switching losses are the dominating factors in power conversion applications. These factors can be controlled at technology development or at IC design with different trade-offs. In this paper we introduce a technique to measure safe operating area (SOA) under high frequency switching conditions – primarily, when the power LDMOS body diode is undergoing reverse-recovery. We show that this new SOA is more conservative than the electrical SOA and defines a diminished boundary for high frequency and high reverse injection operations. With this technique we look at the impact on specific design parameters in commonly used LDMOS topologies in an advanced BCD technology. Furthermore with the help of numerical simulations and careful metrological observations we discuss the phenomena leading to device performance limits useful for IC and device designers. Failure analysis of devices at product level and controlled failures created in standalone devices at wafer-level are examined.


9:50 a.m.

10:20 a.m.

6A.4 Modeling Feedback Effects in Metal Under ESD Stress

T. Maloney, Intel Corporation

The feedback model of on-chip interconnect metal heating during electrostatic discharge (ESD) is extended to capture and simplify overall behavior of the metal. Of greatest interest to risk assessment is the peak temperature Tmax reached during an ESD event, and it is discovered that Tmax for Human Body and Charged Device Model (HBM, CDM) events follows its own simplified feedback equation with constant parameters. These constants are a function of the electrical and thermal properties of the metal layer. The result is a simple relation between Tmax and current density for the HBM or CDM event under consideration, a valuable aid to risk assessment and design rule checks. The summary equations capture the results of many detailed finite element and numerical convolution calculations of heat flow for on-chip metal.

10:45 a.m.

6A.5 Latchup Holding Voltages and Trigger Currents in a SOI Technology

G. Quax, T. Smedes, *NXP Semiconductors

This paper investigates holding voltages and trigger currents in a Silicon-on-Insulator technology. These parameters can be used in automated layout checks. Via a new measurement method, where the well-bias of the test structures is varied with regard to the bias of the emitters of the thyristor, a strong dependency on the emitter distance, and a weak dependency on the well tap distance is observed. The holding voltages are compared to a low-Ohmic and high-Ohmic variant of the same technology node. Trigger currents of a layout with a variable well tap length are investigated. A model for the effective resistance is developed, incorporating the increased resistance for longer current paths by segmenting the current flow area. The performance of the model and possible applications are discussed.

11:10 a.m.

6A.6 Experimental Study of Supply Voltage Stability during ESD (Late News)

Y. Xiu, R. Mertens, N. Thomson, E. Rosenbaum, University of Illinois at Urbana-Champaign

On-chip power supply integrity may be compromised during a power-on ESD event, e.g. system-level ESD. Experimental data are provided to show that the supply integrity is a function of the rail clamp gain, its speed of response to ESD, and the amount of on-chip supply decoupling capacitance. It is also demonstrated that just a few nH of package inductance can cause the on-chip supply to briefly collapse, regardless of the rail clamp response speed.