IRPS

Session 5C – Soft Errors

Session 5C – Soft Errors

Session Co-Chairs: Balaji Narasimham, Broadcom, Ethan Cannon, Boeing
Section F/G

1:55 p.m. – Session Introduction

2:00 p.m.

5C.1 Muon-induced Soft Errors in 16-nm NAND Flash Memories

M. Bagatin, S. Gerardin, A. Paccagnella, A. Visconti*, S. Beltrami*, M. Bertuccio*, K. Ishida**, C. Frost, A. Hillier***, V. Ferlet-Cavrois^, University of Padova, *Micron Technology Inc., **RIKEN Nishina Center, ***STFC Rutherford Appleton Laboratory, ^ESA ESTEC, TEC-QEC

Flash memories based on the floating gate architecture are sensitive to ionizing radiation at sea level, including atmospheric neutrons and alpha particles. No data in the literature are available on the sensitivity of Flash memories to muons. These particles, although very lightly ionizing, are the most abundant at sea level and have been reported to cause upsets in advanced SRAMs through direct ionization. The purpose of this contribution is to present the first experimental investigation of single event upsets induced by muons in 16-nm NAND Flash memories, using accelerated tests. The experimental results are discussed in terms of threshold voltage shifts and raw bit errors, showing that muon-induced upsets are indeed possible also in Flash memories.The threshold LET value for advanced samples is finally analyzed.

2:25 p.m.

5C.2 Impact of Alpha-Radiation on Power MOSFETs

G. Schindler, K.-H. Bach, P. Nelle, M. Deckers, A. Knapp, K. Ermisch, C. Feuerbaum, W. v. Emden*, Infineon Technologies, *Robert Bosch GmbH

In this paper it is shown how the impact of alpha particles in the gate oxide of a power MOSFET leads to a local reduction of the threshold voltage Vth. Evidence is presented that radioactive impurities in the mold compound or solder material of the package indeed are the root cause for such effects observed in long term measurements with electrical gate bias. Furthermore the influence of alpha impacts on application and reliability is investigated.

2:50 p.m.

5C.3 Temperature Dependence of Soft-Error Rates for FF designs in 20-nm Bulk Planar and 16-nm Bulk FinFET Technologies

H. Zhang, H. Jiang, T. Assis*, D. Ball, K.Ni, J. S. Kauppila, R. Schrimpf, L. Massengill, B. Bhuva, B. Narasimham**, S. Hatami**, A. Anvar**, A. Lin**, J. K Wang**, Vanderbilt University, *Robust Chip, Inc, **Broadcom Corporation

Alpha particle-induced flip-flop soft-error rates (SER) for 20-nm bulk planar and 16-nm bulk FinFET technologies are characterized over temperature with different supply voltages. Experimental results indicate that the 16-nm FinFET SER show negligible change with temperature while the 20-nm planar SER increase ~2x over the same temperature range.