IRPS

Session 5B – Interconnect Metallization Reliability

Session 5B – Interconnect Metallization Reliability

Session Co-Chairs: Feng Xia, Intel, Ki-Don Lee, Samsung
Section E

1:55 p.m. – Session Introduction

2:00 p.m.

5B.1 Thermal Characterization and Challenges of Advanced Interconnects (Invited)

B. Li, A. Kim, C. Christiansen*, R. Dufresne*, C. Burke*, D. Brochu*, IBM Systems, *Globalfoundries

Technology scaling and driving to high performance have led to more joule heating in both devices and interconnects. Since temperature is one of the most sensitive factors impacting interconnect reliability, this paper focuses on the thermal characteristics of metal lines with different geometries and surroundings to accurately assess local temperature of different circuit designs. The experimental results reported can be used as basic input parameters and calibration baseline for thermal model development and simulations.

2:25 p.m.

5B.2 Electromigration Failure of Circuit Interconnects

M.-H. Lin, A. Oates, TSMC

The analysis of steady-state stress can accurately predict the locations of electromigration vulnerabilities in multi-segment. The presence of active sinks and reservoirs significantly reduce failure times of short-length conductors. Electromigration failures are found at either the first cathode via in sink/reservoir segments or common-via region, where is correlated with locations of maximum stress.

2:50 p.m.

5B.3 1/f Noise Measurements for Faster Electromigration Characterization

S. Beyne, K.Croes, I. De Wolf, Z. Tőkei, IMEC

The application of 1/f noise measurements to speed up electromigration (EM) testing and provide a better understanding of the underlying mechanisms of electromigration in advanced microelectronics interconnects is investigated. It is shown that 1/f noise measurements can be used for early EM damage detection during EM stress, before any changes in the resistance of the sample are observable. Also, the temperature dependence of the low frequency noise is used to calculate activation energies, which are then demonstrated to be similar to values found for electromigration using standard EM tests. Furthermore, the 1/f noise technique is used to assess and compare the EM properties of various advanced integration schemes and different materials. The 1/f noise measurements provide new evidence for the importance of grain boundary diffusion as a dominant EM failure mechanism in highly scaled
interconnects.

3:45 p.m.

5B.4 Engineering the Failure-Free Lifetime for Cu Vias

G. Hall, D. Allman, M. Eda, T.F. Long, II, *ON Semiconductor

Ensuring the reliability of dual-damascene/low-k back-endof- line (BEOL) metallization requires predictive accelerated failure time (AFT) models of stress migration (SM) and stress induced voiding (SIV). High Temperature Storage (HTS) tests have indicated that competing rates of diffusion and stress build-up leads to a generalized Eyring
model, of the AFT. While the model describes SM qualitatively well, it cannot predict quantitatively the inverse-bathtub shape of the distribution of SIV failures in experiment, and the impact of factors such as linewidth, microstructure, and the non-local nature of void interactions and vias. A more complete model is discussed here, which addresses the shortcomings of all previous approaches to SIV, and can be used to model SIV failures to identify design and process conditions which have a failure-free lifetime (FFL). A surprising novelty of the approach is that the physics of stress relaxation leads us to scaling functions which focus on the right-hand side of the distribution, rather than the usual left/early failures.

4:10 p.m.

5B.5 Influence of Metallization Layout on Aging Detector Lifetime under Cyclic Thermo-Mechanical Stress

G. Pham, M. Ritter, M. Pfost*, Reutlingen University, *University of Innsbruck

The influence of the layout on early warning detectors in BCD technologies for metallization failure under cyclic thermo-mechanical stress was investigated. Different LDMOS transistors, with narrow or wide metal fingers and with or without embedded detectors, were used. The test structures were repeatedly stressed by pronounced self-heating until failure (a short circuit) was detected. The results show that the layout of the on-chip metallization has a large impact on the lifetime. A significant influence of the detectors on the lifetime was also observed, in our case causing a reduction of more than a factor of two, but only for the test structure with narrow metal fingers. The experimental results are explained by an efficient numerical thermo-mechanical simulation approach, giving detailed insights into the strain distribution in the metal system. These results are important for aging detector design and, morever, for LDMOS on-chip metal layout in general.