Session 5A – Transistor Reliability
Session 5A – Transistor Reliability
Session Co-Chairs: Jason Campbell, NIST, Barry Linder, IBM
1:55 p.m. – Session Introduction
5A.1 Reliability of Single-Layer MoS2 Field-Effect Transistors with SiO2 and hBN Gate Insulators
Y. Illarionov, M. Waltl, M. M. Furchi, T. Mueller, T. Grasser*, TU Wien
We perform a detailed study of both hysteresis and bias-temperature instabilities (BTI) in single-layer MoS2 FETs with SiO2 and hBN insulators and capture the correlation between these phenomena. We show that our transistors exhibit a better hysteresis and BTI stability than similar devices reported previously. Moreover, we demonstrate that using of hBN as a gate insulator reduces the impact of slow traps and improves the BTI reliability, while the hysteresis for MoS2/hBN FETs is dominated by ultra-fast traps. However, at higher temperature the BTI reliability of hBN gate insulator is reduced due to thermally activated charge trapping.
5A.2 Nondiffusive Heat Dissipation from a Pulse-Heated Conductive Filament in RRAM (Invited)
K. Regner, J. A. Malen Carnegie Mellon University
Here, we discuss experimental and theoretical studies of nondiffusive thermal transport, which occurs when geometrical length scales are comparable to energy carrier mean free paths (MFPs). We expand upon a previous study that emphasizes the importance of nondiffusive thermal transport in resistive-switching random access memory (RRAM). To model this behavior, an approximate solution to the Boltzmann transport equation (BTE), under the relaxation time approximation in the cylindrical geometry, is derived for the case of an arbitrary, temporally periodic surface temperature boundary condition. This boundary condition coupled with the BTE more realistically models switching stimuli in an RRAM device.
5A.3 Fundamental Study of the Apparent Voltage-dependence of NBTI Kinetics by Constant Electric Field Stresses in Si and SiGe Devices
S. Mukhopadhyay, J. Franco, A. Chasin, P. Roussel, B. Kaczer, G. Groeseneken, N. Horiguchi, D. Linten, A. Thean, imec
The standard BTI time-to-failure (TTF) extrapolation used in industrial R&D is based on simple power-law acceleration models for both time- and voltage-dependences. This approach implicitly assumes the time- and voltage-dependences to be mutually uncorrelated, i.e., the time acceleration exponent (n) is assumed to be a constant, independent of the considered stress voltage range, and vice versa, the voltage acceleration exponent is independent of the considered stress test duration. However, for Ge,SiGe and even for Si, for both planar and finFET devices, the NBTI time exponent has been observed to reduce for increasing stress voltages. This poses concerns for device lifetime extrapolation and for correct reliability benchmarking across different gate stacks.This work brings out the challenges
of the standard BTI TTF extrapolations based on simple power-laws for cross comparison of different technologies. When standard constant voltage stress are performed, field reduction effect can be more severe in some technologies, and voltage dependent time evolutions can cause anomaly in TTF prediction. A novel constant-field experiment has been implemented. This approach revealed an intrinsic uncorrelated nature of time-dependence with stress voltage. This approach can be used for a fair cross-comparison of different technology, avoiding the different impact of field reduction on different device families.
5A.4 Hot Carrier Stress: Aging Modeling and Analysis of Defect Location
G. Torrente; X. Federspiel, D. Rideau, F. Monsieur, C. Tavernier, J. Coignus*, D. Roy, G. Ghibaudo**, STMicroelectronics, *CEA, LETI, **IMEP-LAHC
In this paper a complete TCAD model addressing Hot Carrier Degradation for Flash technology is presented and its validity range extended respect to our previous work. Using electrical parameter correlation, a simple technique for the analysis of trap distribution location is presented and insights at different stress conditions are provided.