Session 4C – Design for Circuit Reliability

Session 4C – Design for Circuit Reliability

Session Co-Chairs: Kevin Cao, Arizona State University, Jim Tschanz, Intel
Section F/G

8:30 a.m. – Session Introduction

8:35 a.m.

4C.1 Timing Characterizations of Device and CPU-like Circuit to Ensure Process Reliability

M.-H. Hsieh, T.-Y. Yew, Y.-C. Huang, W. Wang, N. H. Tseng, W. S. Chou Lee, Y.-H. Lee, TSMC

Existing methodology and stress conditions are ideal for process benchmarking but might not be sufficient under fierce competition between advanced technology development approaches. In this paper, the importance of timing delay characterization in both device and circuit level is demonstrated and emphasized. Due to the difficulties of having accurate aging model for product level simulation during early stage of process development, silicon to simulation (S2S) correlation should be established in circuit level. Experiments in this study cover from discrete device, ring oscillator (RO) and a circuit block from ARM CPU. Based on the extensive results, the characterization of timing margin is highly recommended. So, early warnings of circuit reliability risk can be obtained to save major detours during technology development.

9:00 a.m.

4C.2 Budget-Based Reliability Management to Handle Impact of Thermal issues in 16nm Technology

J.-G. Ahn, J. Cooksey, N. Navale, N. Lo, P.-C. Yeh, J. Chang, Xilinx

We handle the thermal impact on FEOL and BEOL reliability by using new aging simulation flow and EM checking flow which is considering thermal coupling effects. We demonstrated how the budget-based reliability check works with thermal issues and showed that it checks product risk more rigorously. It leads to huge benefit to circuit designers by allowing higher temperature increase both for FINFET SHE and metal wire JHE.

9:25 a.m.

4C.3 Mission Profile Recorder: An Aging Monitor for Hard Events

S. Mhira, V. Huard, A. Jain, F. Cacho, D. Meyer, S. Naudet, A. Bravaix*, C. Parthasarathy, STMicroelectronics, *IM2NP-ISEN

Overall, in this work, we have demonstrated the fundamental as-pects of Mission Profile Recording as an alternative to intrusive, aging monitoring systems to cope with oxide breakdown and elec-tromigration. We have designed, implemented and fully tested on several wafers a functional prototype to achieve a full proof-of-concept. The key element for accurate lifetimes is the accuracy of the Analog-to-Digital Conversion including the process variations and across the temperature and voltage product range. This study offers new perspectives towards product hardening and qualification with respect to an adaptive approach to real user-based workloads.


9:50 a.m.

10:20 a.m.

4C.4 Analog-circuit NBTI Degradation and Time-dependent NBTI Variability: An Efficient Physics-Based Compact Model

K.-U. Giering, G. Rott*, G. Rzepa*, H. Reisinger**, A. K. Puppala, T. Reich, W. Gustin**, T. Grasser*, R. Jancke, Fraunhofer IIS/EAS, *TU Wien, **Infineon

We experimentally and theoretically investigate the NBTI degradation of pMOS devices due to analog stress voltages and thus go beyond existing NBTI studies for digital stress. As a result, we propose a physics-based compact model for analog-stress NBTI which builds upon the extensive TCAD analysis of our ultra-short-delay experimental data. The numerical efficiency of the compact model allows its direct coupling to electric circuit simulators and permits to accurately account for NBTI degradation already during circuit design. Our model enables the calculation of the time-dependent NBTI variability of single device parameters and of circuit performance parameters. We demonstrate the NBTI model on an operational amplifier and calculate the mean drift and variability of its offset voltage.

10:45 a.m.

4C.5 New Methodology for On-Chip RF Reliability Assessment

L. Heiß, A. Lachmann*, R. Schwab*, G. Panagopoulos*, P. Baumgartner*, M. Y. Virupakshappaa, D. Schmitt-Landsiedel, Technical University of Munich, *Intel Deutschland GmbH

On-chip self-stressing circuits are gaining increasing interest to study frequency dependency of transistor reliability. Thereby observation of frequency dependent degradation in experimental results can have two origins: (1) A physical root cause, i.e. the considered degradation mechanism is indeed frequency dependent. (2) Insufficient signal integrity, particularly at high frequencies. Former work mainly focused to explain experimental results in the sense of (1), but has neglected (2). This work presents a new approach which uses an advanced test structure to investigate the signal integrity of on-chip stress circuits. Experimental results from a 28nm HKMG technology show that this method considerably supports the interpretation of RF reliability data which can otherwise easily be misinterpreted.

11:10 a.m.

4C.6 Reliability vs. Secuirty: Challenges and Opportunitues for Developing Reliable and Secure Integrated Circuits (Invited)

F. Rahman, D. Forte, M. Tehranipoor, University of Florida

As technology further scales, devices offer better performance with faster speed and lower power albeit at the cost of reliability. Advanced technology nodes introduce higher variations in manufacturing processes, and devices experience greater aging and environmental degradation. Although such reliability issues should be suppressed for the sake of performance in both CMOS and post-CMOS devices, researchers have leveraged them for a variety of applications and unique primitives for hardware-oriented security. In this paper, we present a comprehensive study on device reliability and security, and make a qualitative assessment of different variability and degradation sources based on their impact on performance, reliability and security. We conclude that reliability and security both play vital roles for respective applications and must be treated in a holistic manner. Hence we urge the reliability and security communities to work together to develop new technologies for designing high performance, reliable and secure integrated circuits.