IRPS

Session 4B -Process Integration

Session 4B -Process Integration

Session Co-Chairs: Bill McMahon, Intel, Siddarth Krishnan, Applied Materials
Section E

8:30 a.m. – Session Introduction

8:35 a.m.

4B.1 Process Optimizations for NBTI/PBTI for Future Replacement Metal Gate Technologies

B. Linder, A. Dasgupta, T. Ando, E. Cartier, U. Kwon, R. Southwick, M. Wang, S. Krishnan, M. Hopstaken, M. Bajaj, R. Pandey, W. Chang, T. Yamashita, O. Gluschenkov, V Narayanan, J. Stathis, S. Ray*, J. Liu*, IBM, *Global Foundries

Bias Temperature Instability (BTI) continues to be a major reliability concern and is the limiting mechanism for inversion thickness (Tinv) scaling for future technologies. Replacement Metal Gate (RMG) technologies present unique challenges for improving NBTI and PBTI as compared to traditional Gate First technologies, where the gate stack is exposed to the high temperature source/drain (s/d) anneal. We have identified four methods for improving BTI in RMG technologies: structural optimization of the gate stack within RMG thermal constraints, layer thicknesses optimization, defect control by introducing dopants into the dielectric stack, and metal workfunction (WF) modulation that provides BTI-benefits which exceed predictions by a simple effective field consideration.

9:00 a.m.

4B.2 NBTI in Replacement Metal Gate SiGe core FinFETs: Impact of Ge Concentration, Fin Width, Fin Rotation and Interface Passivation by High Pressure Anneals

J. Franco, B. Kaczer, A. Chasin, H. Mertens, L.-Å. Ragnarsson, R. Ritzenthaler, S. Mukhopadhyay, H. Arimura, P. Roussel, E. Bury, N. Horiguchi, D. Linten, G. Groeseneken, A. Thean, Imec

We report a broad study of NBTI in RMG SiGe core FinFETs, focusing on the impact of Ge concentration (0%, 25% and 45%), fin width (1um–>20nm), fin side-wall orientation (<110> and <100>, obtained by 45° fin rotation), and interface passivation by high pressure anneals (HPA). We focus on Si-cap-free gate stacks which offer simplified FinFET integration. Direct oxidation of SiGe yields poor interface quality, which can be restored by HPA. Despite a wide distribution of defect levels in the interfacial layer due to Ge suboxide formation, SiGe reliability still benefits of a reduced bulk oxide trapping thanks to favorable energy decoupling of channel carriers to dielectric defect levels. Further NBTI improvement is observed thanks to oxide field reduction in fully depleted fins. Fin rotation does not improve NBTI in SiGe fins, while some improvement, particularly of the near-channel degradation, was obtained by HPA. Based on these results we conclude that Si-cap-free RMG SiGe gate stacks with properly optimized HPA can offer a simplified FinFET integration, with a limited NBTI reliability penalty compared to best-in-class Si-passivated SiGe devices.

9:25 a.m.

4B.3 Study of Oxygen Vacancy in High-k Gate Dielectric by Charge Injection Technique

J. Liao, S.-H. Gao, K. Joshi, Y.-H. Lee, T.L. Lee, H.S. Wang, S.Y. Chien, J.-S. Wang, J.-R. Shih, K. Wu, Taiwan Semiconductor Manufacturing Company

A new technique by charge injection is introduced to investigate the charging effect on weak oxide in the gate stack of high-k metal gate process. The oxide with extra oxygen vacancy are more vulnerable to process charging, as verified by the correlation of Vt vs. subthreshold swing degradation, SILC spectrum, and chemical bonding state analysis using X-ray photoelectron spectroscopy (XPS) and electron energy loss spectroscopy (EELS). Degradation of pFET threshold voltage (Vt) shift by gate injection under Source/Drain (S/D) floating condition is observed, this is attributed to the oxide damage by the accelerated hot carriers from S/D reverse bias. The convolution of “random dopant fluctuation (RDF) + charging effect” is expected to magnify devices Vt shift, especially for those worse bit cells with high Vt as verified by the Monte-Carlo simulation. We further demonstrate that process with tighten Vt distribution, such as FinFET technology with less implant process and better charge release immunity, is less vulnerable to the charging induced Vt shift.

Break

9:50 a.m.

10:20 a.m.

4B.4 Hot-carrier Analysis on nMOS Si FinFETs with Solid Source Coped Junction

A. Chasin, J. Franco, R. Ritzenthaler, G. Hellings, M. Cho, Y. Sasaki, A. Subirats, P. Roussel, B. Kaczer, D. Linten, N. Horiguchi, G. Groeseneken, A. Thean, imec

We report extensive experimental results of the Channel Hot Carrier (CHC) and Positive Bias Temperature Instability (PBTI) reliability of nMOS Si bulk-FinFETs with extension doping by PEALD Phosphorus doped Silicate Glass (PSG). Device performance improvements with PSG doping are achieved without substantial device reliability degradation even for short channel FinFETs. PSG results in less damage in the junctions and lower Gate Induced Drain Leakage (GIDL) current than standard Phosphorous Ion Implantation process (P I/I).

10:45 a.m.

4B.5 Transistor Reliability Characterization and Comparisons for a 14 nm Tri-gate Technology Optimized for System-on-Chip and Foundry Platforms

C. Prasad, K. W. Park, P. Bai, H.-Y. Chang, M. Chahal, N. Dias, W. Hafez, C.-H. Jan, I. Meric, N. Nidhi, S. Novak, R. Olac-vaw, R. Ramaswamy, S. Ramey, C. Tsai, Intel Corporation

The transistor reliability characterization of a 14nm SoC node optimized for low power operation is described. In-depth assessment of reliability vs. performance benefit for Core and I/O devices are performed on Logic and SoC nodes, and clear trends with scaling are identified. Insight is provided into hot carrier and off-state aging, and self-heat. The 14nm SoC node is shown to be robust for all transistor reliability modes. Process monitor data are used to demonstrate a stable line in high-volume manufacturing.