IRPS

Session 4A – Compound/Opto Electronics

Session 4A – Compound/Opto Electronics

Session Co-Chairs: Jungwoo Joh, Texas Instruments, Toshi Kikkawa, Transphorm
Section D

8:30 a.m. – Session Introduction

8:35 a.m.

4A.1 Negative-Bias Temperature Instability of GaN MOSFETs

A. Guo, J. del Alamo, MIT

GaN high-electron-mobility transistors with insulated-gate (MIS-HEMTs) are attractive alternatives to Si for power electronics. Compared to the traditional HEMT structure with Schottky gate, GaN MIS-HEMTs offer low gate leakage current, higher breakdown voltage, and possible enhancement-mode operation, all desirable attributes for power electronics. However, reliability issues surrounding GaN-HEMTs, especially the threshold voltage instability under high voltage stress, represent a major roadblock for technology commercialization. The origin of this problem in GaN MIS-HEMTs is not well understood because the gate stack has many layers and interfaces that present many opportunities for trapping and complex dynamics. We isolate the contribution of the gate dielectric and its interfaces by studying a simple GaN MOSFET structure. This device approach, in its own right, is also a strong candidate for power electronic applications. We identified three degradation mechanisms that are responsible for NBTI in oxide/GaN MOSFETs. Under benign stress, recoverable electron detrapping from pre-existing oxide traps close to the oxide/GaN interface takes place shifting VT negative. Under moderate stress, an additional transient positive VT shift is caused by electron trapping into defects in the buffer layer. Under harsh stress conditions there is also a permanent negative VT shift and permanent degradation in gm and S that is the result of interface state generation. These studies should be instrumental in understanding the more complex instability issues of GaN MIS-HEMTs. The full-length paper will present the model and experimental procedures in more detail.

9:00 a.m.

4A.2 Positive Bias Temperature Instability Evaluation in Fully Recessed Gate GaN MIS-FETs

T.-L. Wu, J. Franco, D. Marcon, B. De Jaeger, B. Bakeroot, X. Kang, S. Stoffels, M. Van Hove, G. Groeseneken, S. Decoutere, imec

GaN-based devices are promising candidates for power switching applications. D-mode AlGaN/GaN MIS-HEMTs or e-mode recessed gate GaN MIS-FETs attract a lot of attentions recently. However, the reliability remains a big challenge on such architectures due to an non-native gate dielectric on top of the AlGaN barrier or GaN channel, leading to VTH hysteresis after a forward-reverse gate bias sweep or VTH shift during a positive gate bias stress, which is generally called positive bias temperature instability (PBTI). In this paper, we study PBTI in fully recessed gate GaN MIS-FETs. Unlike similar PBTI studies in GaN literature, we use the eMSM (extended-Measurement-Stress-Measurement) technique to perform a set of stress/recovery tests to evaluate the PBTI phenomena with collecting the maximum information during the stress and relaxation period. Furthermore, we propose a physical model to explain the results.

Break

9:50 a.m.

9:55 a.m.

4A.3 Product Reliability of GaN Devices (Invited)

S. Bahl, D. Ruiz, D. S. Lee, Texas Instruments

To enable the widespread adoption of GaN products, the industry needs to be convinced of product-level reliability. The difficulty with product-level reliability lies with the diverse range of products and use conditions, a limited ability for system-level acceleration, and the complication from non-GaN system failures. For power management applications, however, it is possible to identify fundamental switching transitions. This allows the device to be qualified in an application-relevant manner. In this paper, we explain how hard-switching can form a fundamental switching transition for power management products. We further show that the familiar double-pulse tester is a good hard-switching qualification test vehicle. The methodology is explained in the context of the existing qualification framework for silicon transistors.

10:20 a.m.

4A.4 Impact of Buffer Charge on the Reliability of Carbon Doped AlGaN/GaN-on-Si HEMTs

I. Chatterjee, M. Uren, S. Karboyan, S. M. Horcajo, A. Pooth, K. B. Lee*, Z. Zaidi*, P. Houston*, D. Wallis**, I. Guiney**, C. Humphreys**, M. Kuball, University of Bristol, *The University of Sheffield, **University of Cambridge

Charge trapping and transport in the carbon doped GaN buffer of an AlGaN/GaN-on-Si HEMT has been investigated. Back-gating and dynamic RON experiments show how the onset of leakage in the strain relief layer at a lower field than that through the upper part of the structure can result in serious long-term trapping leading to current collapse under standard device operating conditions. Controlling current-collapse requires control of not only the layer structures and its doping, but also the precise balance of leakage in each layer.

10:45 a.m.

4A.5 Understanding the Degradation Sources Under ON-state Stress in AlGaN/GaN-on-Si SBD: Investigation of the Anode-Cathode Spacing Length Dependence

A. N. Tallarico, P. Magnone*, S. Stoffels**, S. Lenci**, D. Marcon**, E. Sangiorgi, S. Decoutere**, C. Fiegna**, University of Bologna, *University of Padova, **imec

In this paper, we report an analysis of the degradation induced by ON-state stress in Au-free AlGaN/GaNon- Si Schottky barrier diodes (SBDs). When the device operates in ON-state mode, the combined effect of large currents and moderate electric fields may cause a shift of the turn-on voltage (VTON) and ON-resistance (RON) because of the charge carrier trapping/de-trapping, occurring in different regions and related to different types of defects. In particular, the influence of the anode-cathode spacing length on the ON-state degradation has been investigated and the degradation sources, attributable to ΔVTON and ΔRON, have been understood. Moreover, thanks to this approach, a critical electric field for the RON degradation has been reported.

11:10 a.m.

4A.6 Progressive Breakdown in High-Voltage GaN MIS-HEMTs

S. Warnock, J. del Alamo, Massachusetts Institute of Technology

As the demand for more energy efficient electronics increases, GaN Field-Effect Transistors (FETs) have emerged as promising candidates for high-voltage power management applications. Though GaN has excellent material properties, there are still many challenges to overcome before GaN power transistors are ready for commercial deployment. Our work focuses on gate dielectric reliability and in particular, in contributing fundamental understanding behind the physics of time-dependent dielectric breakdown (TDDB) of the gate dielectric in GaN MIS-HEMTs. In this work we investigate progressive breakdown (PBD). We have found classic features resembling those observed in silicon devices. That is, we see evidence to support the percolation model of defects, both in the breakdown statistics but also in the distribution of breakdown location throughout the dielectric. We also see an increase in gate leakage in current-voltage characterization after PBD has occurred, with voltage and temperature dependences that are consistent with observed behavior in silicon. This classic TDDB behavior gives hope that a lifetime model for TDDB in GaN MIS-HEMTs can be developed.