Session 3B- Joint Soft Errors/ESD and Latch-up
Session 3B- Joint Soft Errors/ESD and Latch-up
Soft Errors Session Chairs: Balaji Narasimham, Broadcom, Ethan Cannon, Boeing
ESD and Latch-up Session Chairs: Teruo Suzuki, Socionext, Dimitri Linten, imec
1:55 p.m. – Session Introduction
3B.1 Extreme Scale and Bleeding Edge Technology Lead to a Need for Resilient High Performance Computing Systems (Invited)
N. DeBardelebren, Los Alamos National Laboratory
High Performance Computing (HPC) and supercomputing are an important sector of the computing field. Distinguishing itself from cloud computing, HPC systems are sized to run extremely large and important calculations such as tightly coupled numerical simulations. These often run for days to weeks on supercomputers and are used to inform scientific discovery and national security. It comes as no surprise then that reliable HPC systems are integral to producing believable scientific results. In this paper we build on years of experience studying supercomputers around the U.S. Department of Energy (DOE) and bring together insights about challenges and needs for HPC reliability. First, we discuss the state of the practice in HPC reliability. We look at a sampling of results from previous work and how reliability telemetry data is used by vendors, system architects, and end users. Finally, we discuss some changes coming in the next decade for HPC systems and how the technology we depend on will drive new reliability challenges that must be addressed and monitored.
3B.2 SE Performance of a Schmitt-Trigger-Based-D-Flip-Flop Design in a 16-nm Bulk FinFET CMOS Process
H. Jiang, H. Zhang, D. R. Ball, L. Massengill, B. Bhuva, T. Assis*, B. Narasimham**, Vanderbilt University, *Robust Chip, Inc., **Broadcom Corporation
A har+I130:AJ143dened Flip-Flop (FF) design using Schmitt trigger circuits for improved soft error (SE) performance is presented. The Schmitt-trigger DFF (STDFF) design along with conventional DFF in a 16-nm bulk FinFET CMOS process were tested using alpha particles and heavy-ions. The STDFF design shows 162× improvement in the alpha SER and upto 30× improvement in heavy-ion cross-section compared with conventional DFF at nominal supply voltage.
3B.3 Hardware Based Empirical Model for Predicting Logic Soft Error Cross-section
S. Jagannathan, N. Mahatme, N. J. Gaspard*, B. Bhuva*, L. Massengill*, Thomas Loveless**, Freescale Semiconductor, *Vanderbilt University, **University of Tennessee
This work presents a technique to estimate logic cross-section using measured single-event transient pulse widths from radiation experiments. The results are verified by comparing against direct measurement of logic cross-section using C-CREST circuit. Since the logic cross-section is extracted based on experimentally measured transients, it includes device level effects and could be used by existing software-based methods to accurately predict logic soft error rate.
3B.4 Investigation of Logic Circuit Soft Error Rate (SER) in 14nm FinFET Technology
T. Uemura, S. Lee, S. Pae, J. Park, H. Lee, Samsung Electronics
This paper presents characterization results of soft error rate (SER) on logic circuits manufactured with 14 nm High-k/metal gate bulk FinFET technology. The FinFET SER advantage seen on SRAM was also validated on logic circuits (5-10X improvement). Adding NMOS on low critical charge can increase error rate, yet it can be easily mitigated by the design change. Design schemes for low-power has little impact to the SER. Single event transient on clock-line in 14 nm FinFET was substantially improved from planer-MOS.
3B.5 Bidirectional NPN ESD Protection in Silicon Photonics Technology
R. Boschke, S.-H. Chen*, M. Scholz*, G. Hellings*, P. De Heyn*, P. Verheyen*, J. Van Campenhout*, D. Linten*, A. Thean*, G. Groeseneken, KU Leuven, *IMEC
Silicon photonics technologies are used for low power, high bandwidth signal transfer between CMOS chips. Silicon waveguides transfer the optical signal while Silicon modulators (Si MOD) and Germanium photodetectors (Ge PD) convert the electrical into an optical signal and vice versa. Ge PDs and Si MOD need ESD protection to survive S20.20 controlled assembly. A NPN transistors, that was integrated into the technology, can provide an effective and transparent ESD protection. TLP IV of the NPN show a snapback and an S-bent that is explained and verified with TCAD.
3B.6 Systematic Transient Characterization of Graphene Interconnects for on-Chip ESD Protection
Q. Chen, R. Ma, F. Lu, C. Wang, M. Liu, A. Wang, W. Zhang*, M. Xia*, Y.-H. Xie*, Y. Cheng**, University of California, Riverside, *University of California, Los Angeles, **Peking University
We report comprehensive transient characterization of graphene ribbons (GR) for ESD protection circuits by TLP testing with varying ESD pulse rise time and duration across -10ºC to 110ºC. Practical GR dimensions and large number statistics provide practical design guidelines for on-chip ESD circuits using robust GR interconnects.