IRPS

Session 2A – Transistor Reliability

Session 2A – Transistor Reliability

Session Co-Chairs: Jason Campbell, NIST, Barry Linder, IBM
Section D

10:45 a.m. – Session Introduction

10:50 a.m.

2A.1 The “Permanent” Component of NBTI Revisited: Saturation, Degradation-Reversal, and Annealing

T. Grasser, M. Waltl, G. Rzepa, W. Goes, Y. Wimmer, A.-M El-Sayeed*, A. L. Shluger*, H. Reisinger**, B. Kaczer***, TU Wien, *University College London, **Infineon, ***imec

While the defects constituting the recoverable component R of NBTI have been very well analyzed recently, the slower defects forming the more “permanent” component P are much less understood. Using a pragmatic definition for P, we study the evolution of P at elevated temperatures to accelerate these very slow processes. We demonstrate for the first time that P not only clearly saturates, with the saturation value depending on the gate bias, but also that the degradation at constant gate bias can also slowly reverse. Furthermore, at temperatures higher than about 300C, a significant amount of additional defects is created. Our new data are consistent with a recently suggested hydrogen release model which will be studied in detail using newly acquired long-term data.

11:15 a.m.

2A.2 Hot Carrier Reliability Characterization in Consideration of Self-Heating in FinFET Technology

M. Jin, C. Liu, J. Kim, S. Choo, Y. Kim, H. Shim, L. Zhang, K. Nam, J. Park, S. Pae, . Lee, Samsung Electronics

The severity of hot carrier injection (HCI) in PFET becomes worse than NFET under higher temperatures. This new observation is further found to be due to the coupled self-heating effects (SHE) during DC HCI stress (also the larger Ea in PFET HCI), rather than the negative bias temperature effect (NBTI) mixed components. Furthermore, in order to guarantee the precise estimation of HCI under circuit level AC condition, a new empirical HCI lifetime model with decoupling the SHE is proposed, which is further verified by the Si data from nanosecond pulsed waveform HCI stress and Ring Oscillator level stress.

11:40 a.m.

2A.3 Characterization of Self-heating Leads to Universal Scaling of HCI Degradation of Multi-Fin SOI FinFETs

H. Jiang, S. Shin, X. Liu*, Xing Zhang*, A. Alam, Purdue University, *Peking University

SOI FinFETs and other Gate-all-around (GAA) transistors topologies have excellent 3-D electrostatic control and therefore, have been suggested as potential technology options for sub-14 nm technology nodes. Unfortunately, the narrow gate geometry and reduced gate pitch suppress heat dissipation and increase thermal cross-talk, leading to severe self-heating of these transistors. Self-heating degrades performance and makes the classical reliability theories based on TL~Tsub irrelevant. In this paper, first, we propose a physicsbased thermal circuit compact model for multi-fin SOI FinFETs to characterize self-heating and validate the results by AC conductance method. Next, we analyze HCI radation varying with the number of fin (NFIN), chuck temperature (Tsub) and AC frequency (f). The results show that HCI degradation dependent variables (NFIN, Tsub, f) can be correlated to the lattice temperature (TL= g(NFIN, Tsub, f ) ) and obey the universal degradation curve ( ΔVth(TL) = f(S(TL) × t) ). Si-O bond-dispersion model explains the universal curve; therefore, the model can be used for a long term reliability projection with arbitrary combination NFIN, Tsub, f, etc.