2016 IRPS Tutorials

Sunday

• Morning Break – 10:00 a.m. – 10:15 a.m.
• Lunch – 11:45 a.m. – 1:15 p.m.
• Afternoon Break – 2:45 p.m. – 3:00 p.m.

8:30 a.m. – 10:00 a.m.

Track 1: Technology Section F/G

Introduction to Reliability Physics and Engineering

Joe McPherson – McPherson Reliability Consulting LLC

Track 2: Component Section D

MEMORY 1 – The Physics of Flash Memory Reliability

Riichiro Shirota / Hiroshi Watanabe – National Chiao Tung Univ.

Track 3: System Section E

An Overview of Mechanical Reliability Challenges in Electronics Across Length Scales

Shankar Ganapathysubramanian and Sudarshan Rangaraj – Amazon Lab126

10:15 a.m. – 11:45 a.m.

Track 1: Technology Section F/G

FEOL Reliability – From Dielectric Trap Properties to Degradation Mechanisms and Their Distributions

Ben Kaczer and Robin Degraeve – imec

Track 2: Component Section D

MEMORY 2 – Advanced Memory Technologies: CBRAM and OxRAM

Shosuke Fujii – Toshiba Corp

1:15 p.m. – 2:45 p.m.

Track 1: Technology Section F/G

MOL Process Integration and Reliability Assessment Challenges

Richard Southwick – IBM

Track 2: Component Section D

2.5D PACKAGING – Si Interposer, Heterogeneous Devices

Sam Gu – Qualcomm

Track 3: System Section E

Learning from and Reduction of IC Customer Returns

Fred Kuper and Michael Stevens – NXP Semiconductors

3:00 p.m. – 4:30 p.m.

Track 1: Technology Section F/G

BEOL Reliability – Challenges from Technology Scaling to Chip Design and System Integration

Baozhen Li – IBM

Track 2: Component Section D

3D PACKAGING – Reliability of 3D Through-Silicon-Via (TSV) Technologies

Dimitris P. Ioannou – GlobalFoundries

Track 3: System Section E

SECURITY – What are the interactions between hardware reliability and system security?

Swarup Bhunia – University of Florida

Monday

• Morning Break – 10:00 a.m. – 10:15 a.m.
• Lunch – 11:45 a.m. – 12:45 p.m.

8:30 a.m. – 10:00 a.m.

Track 1: Technology Section F/G

Wafer Level Reliability – Techniques and Models for Determining FEOL/BEOL Failure Mechanisms

Yung-Huei Lee – TSMC

Track 2: Component Section D

CIRCUIT AGING 1 – Optimizing VLSI Circuit Reliability through Presilicon Design and Postsilicon Adaptation

Sachin S. Sapatnekar – University of Minnesota

Track 3: System Section E

Concepts for Managing System Behavior in the Presence of Hardware Faults

Jim Lewis – Oracle America Inc

10:15 a.m. – 11:45 a.m.

Track 1: Technology Section F/G

Challenges in Reliability Evaluations Due to FINFET SelfHeating Effects

Ben Kaczer and Robin Degraeve – imec

Track 2: Component Section D

CIRCUIT AGING 2 – Measurement Techniques

Takashi Sato and Hidetoshi Onodera – Kyoto University

Track 3: System Section E

Soft Errors in Functional and System Safety Standards

Riccardo Mariani – Yogitech SpA

12:45 p.m. – 2:15 p.m.

Track 1: Technology Section F/G

Failure Analysis Techniques

Kevin Johnson – Intel

Track 2: Component Section D

Reliability Differences Between RF and Power Switching GaN Power Transistors

Michael J Uren – University of Bristol

Track 3: System Section E

ESD and EOS Design and Qualification Methods

Charvaka Duvvury – Charvaka Duvvury LLC at ESD Consulting