IRPS Technical Program Schedule

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General Session – Section D/E – 8:00 a.m.
Welcome Remarks – Chris Henderson, Semitracks – 8:10 a.m.
Introduction to Technical Program

Tuesday – 8:30 a.m.

Keynote 1 – Implications for System Reliability in Future Industrial and Automotive Designs, Scott Roller, Vice President Systems Engineering and Marketing, Texas Instruments

Tuesday – 9:15 a.m.

Keynote 2 – Driverless Vehicles? The Journey Ahead, Raj Rajkumar, George Westinghouse Professor, Carnegie Mellon University

Tuesday – 10:00am


Tuesday – 10:15 – Break

Session 2A – Transistor Reliability

Session Co-Chairs: Jason Campbell, NIST, Barry Linder, IBM
Section D

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10:45 a.m. – Session Introduction

10:50 a.m. – 2A.1 The “Permanent” Component of NBTI Revisited: Saturation, Degradation-Reversal, and Annealing

11:15 a.m. – 2A.2 Hot Carrier Reliability Characterization in Consideration of Self-Heating in FinFET Technology

11:40 a.m. – 2A.3 Characterization of Self-heating Leads to Universal Scaling of HCI Degradation of Multi-Fin SOI FinFETs

Session 2B – System Reliability

Session Co-Chairs: Kingsuk Maitra, Microsoft, Werner Kanert, Infineon
Section E

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10:45 a.m. – Session Introduction

10:50 a.m. – 2B.1 Software-based Dynamic Reliability Management for GPU Applications

11:15 a.m. – 2B.2 Time Ordered Events CPU Reliability Assessment

11:40 a.m. – 2B.3 Power-Supply Impact on the Reliability of mid-1X TLC NAND Flash Memories

Session 3A – Dielectric Reliability (Front-end and Back-end)

Session Co-Chairs: Shou-Chung Lee, TSMC, Shinji Yokogawa, Polytechnic University of Japan
Section D

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1:55 p.m. – Session Introduction

2:00 p.m. – 3A.1 Fundamental Statistical Properties of Reconstruction Methodology for TDDB with variability (BEOL/MOL/FEOL) Applications

2:25 p.m. – 3A.2 New Breakdown Mechanism Investigation: Barrier Metal Penetration Induced Soft Breakdown in Low-k Dielectrics

2:50 p.m. – 3A.3 On Why Dielectric Breakdown Strength Reduces With Dielectric Thickness

3:15 p.m. – 3A.4 A New Aspect of Time-dependent Clustering Model for Non-uniform Dielectric TDDB

Break – 3:40 p.m.

4:10 p.m. – 3A.5 Time-Dependent Series Resistance and Implications for Voltage Acceleration Models in BEOL TDDB

4:35 p.m. – 3A.6 A New Model for Dielectric Breakdown Mechanism of Silicon Nitride Metal-Insulator-Metal Structures

Session 3B- Joint Soft Errors/ESD and Latch-up

Soft Errors Session Chairs: Balaji Narasimham, Broadcom, Ethan Cannon, Boeing
ESD and Latch-up Session Chairs: Teruo Suzuki, Socionext, Dimitri Linten, imec
Section E

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1:55 p.m. – Session Introduction

2:00 p.m. – 3B.1 Extreme Scale and Bleeding Edge Technology Lead to a Need for Resilient High Performance Computing Systems (Invited)

2:25 p.m.- 3B.2 SE Performance of a Schmitt-Trigger-Based-D-Flip-Flop Design in a 16-nm Bulk FinFET CMOS

2:50 p.m. – 3B.3 Hardware Based Empirical Model for Predicting Logic Soft Error Cross-section

3:15 p.m. – 3B.4 Investigation of Logic Circuit Soft Error Rate (SER) in 14nm FinFET Technology

Break – 3:40 p.m.

4:10p.m. – 3B.5 Bidirectional NPN ESD Protection in Silicon Photonics Technology

4:35 p.m. – 3B.6 Systematic Transient Characterization of Graphene Interconnects for on-Chip ESD Protection

Session 3C – Photovoltaics Reliability/ESREF Best Paper

Photovoltaics Reliability Session Chairs: Andrea Cester, University of Padova , Michael Daenen, University of Hasselt
Section F/G

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1:55 p.m. – Session Introduction

2:00 p.m. – 3C.1 Predictive Simulation of Defect Migration and Metastabilities in CdTe Solar Cells

2:25 p.m. – 3C.2 Effects of Current Stress and Thermal Storage on polymeric heterojunction P3HT:PCBM Solar Cell

2:50 p.m. – 3C.3 Improvement of Solar Cell Performance and Reversibility of Ageing Effects in Hydrogenated

3:15 p.m. – 3C.4 Reconfigurable Power Management for Monolightic CMOS-on-Photovoltaic under Partial and Complete Shading

Break – 3:40 p.m.

4:10 p.m. – 3C.5 System-level Process-voltage-temperature Variation-aware Reliability Simulator using a Unified Novel Gate-delay Model for BTI, HCI and GOBD (ESREF Best Paper)


Tuesday, April 20, 6:30 p.m – 9:30 p.m.

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WS.1 Transistor/Circuit: Advanced CMOS Nodes (FDSOI, FinFET) usage for High Reliability Markets from Device and Design Perspective

WS.2 – BEOL: Challenges for EM and SM / Test Time / Power Management

WS.3 – Compound: GaN Reliability – What is Missing? What Should be Looked at Beyond What’s Already Known?

WS.4 – System Reliability: Design for Reliability for Internet of Things

WS.5 – Advanced CPI: 2.5/3D Packaging

WS.6 – Memory: Memory Reliability for Automotive Application

WS.7 – MOL Reliability


Session 4A – Compound/Opto Electronics

Session Co-Chairs: Jungwoo Joh, Texas Instruments, Toshi Kikkawa, Transphorm
Section D

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8:30 a.m. – Session Introduction

8:35 a.m. – 4A.1 Negative-Bias Temperature Instability of GaN MOSFETs

9:00 a.m. – 4A.2 Positive Bias Temperature Instability Evaluation in Fully Recessed Gate GaN MIS-FETs

Break – 9:50 a.m.

9:55 a.m. – 4A.3 Product Reliability of GaN Devices (Invited)

10:20 a.m. – 4A.4 Impact of Buffer Charge on the Reliability of Carbon Doped AlGaN/GaN-on-Si HEMTs

10:45 a.m. – 4A.5 Understanding the Degradation Sources Under ON-state Stress in AlGaN/GaN-on-Si SBD: Investigation of the Anode-Cathode Spacing Length Dependence

11:10 a.m. – 4A.6 Progressive Breakdown in High-Voltage GaN MIS-HEMTs

Session 4B -Process Integration

Session Co-Chairs: Bill McMahon, Intel, Siddarth Krishnan, Applied Materials
Section E

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8:30 a.m. – Session Introduction

8:35 a.m. – 4B.1 Process Optimizations for NBTI/PBTI for Future Replacement Metal Gate Technologies

9:00 a.m. – 4B.2 NBTI in Replacement Metal Gate SiGe core FinFETs: Impact of Ge Concentration, Fin Width, Fin Rotation and Interface Passivation by High Pressure Anneals

9:25 a.m. – 4B.3 Study of Oxygen Vacancy in High-k Gate Dielectric by Charge Injection Technique

Break – 9:50 a.m.

10:20 a.m. – 4B.4 Hot-carrier Analysis on nMOS Si FinFETs with Solid Source Coped Junction

10:45 a.m. – 4B.5 Transistor Reliability Characterization and Comparisons for a 14 nm Tri-gate Technology Optimized for System-on-Chip and Foundry Platforms

Session 4C – Design for Circuit Reliability

Session Co-Chairs: Kevin Cao, Arizona State University, Jim Tschanz, Intel
Section F/G

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8:30 a.m. – Session Introduction

8:35 a.m. – 4C.1 Timing Characterizations of Device and CPU-like Circuit to Ensure Process Reliability

9:00 a.m. – 4C.2 Budget-Based Reliability Management to Handle Impact of Thermal issues in 16nm Technology

9:25 a.m. – 4C.3 Mission Profile Recorder: An Aging Monitor for Hard Events

Break – 9:50 a.m.

10:20 a.m. – 4C.4 Analog-circuit NBTI Degradation and Time-dependent NBTI Variability: An Efficient Physics-Based Compact Model

10:45 a.m. – 4C.5 New Methodology for On-Chip RF Reliability Assessment

11:10 a.m. – 4C.6 Reliability vs. Secuirty: Challenges and Opportunitues for Developing Reliable and Secure Integrated Circuits (Invited)


Wednesday, April 20, 12:20 p.m. – 2:15 p.m.

The Future of Machine Brain Interfaces, Sanjay Natarajan, Vice President Technology and Manufacturing Group, Intel Corporation

Session 5A – Transistor Reliability

Session Co-Chairs: Jason Campbell, NIST, Barry Linder, IBM
Section D

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1:55 p.m. – Session Introduction

2:00 p.m. – 5A.1 Reliability of Single-Layer MoS2 Field-Effect Transistors with SiO2 and hBN Gate Insulators

2:25 p.m. – 5A.2 Nondiffusive Heat Dissipation from a Pulse-Heated Conductive Filament in RRAM (Invited)

2:50 p.m. – 5A.3 Fundamental Study of the Apparent Voltage-dependence of NBTI Kinetics by Constant Electric Field

3:45 p.m. – 5A.4 Hot Carrier Stress: Aging Modeling and Analysis of Defect Location

Session 5B – Interconnect Metallization Reliability

Session Co-Chairs: Feng Xia, Intel, Ki-Don Lee, Samsung
Section E

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1:55 p.m. – Session Introduction

2:00 p.m. – 5B.1 Thermal Characterization and Challenges of Advanced Interconnects (Invited)

2:25 p.m. – 5B.2 Electromigration Failure of Circuit Interconnects

2:50 p.m. – 5B.3 1/f Noise Measurements for Faster Electromigration Characterization

3:45 p.m. – 5B.4 Engineering the Failure-Free Lifetime for Cu Vias

4:10 p.m. – 5B.5 Influence of Metallization Layout on Aging Detector Lifetime under Cyclic Thermo-Mechanical Stress

Session 5C – Soft Errors

Session Co-Chairs: Balaji Narasimham, Broadcom, Ethan Cannon, Boeing
Section F/G

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1:55 p.m. – Session Introduction

2:00 p.m. – 5C.1 Muon-induced Soft Errors in 16-nm NAND Flash Memories

2:25 p.m. – 5C.2 Impact of Alpha-Radiation on Power MOSFETs

2:50 p.m. – 5C.3 Temperature Dependence of Soft-Error Rates for FF designs in 20-nm Bulk Planar and 16-nm Bulk FinFET Technologies


WEDNESDAY, April 20, 2016
6:30 p.m. – 9:30 p.m.
Exhibit Hall C

Compound/Opto Electronics

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CD-1 On Conduction Mechanisms through SiN/AlGaN based Gate Dielectric and Assessment of Intrinsic Reliability

CD-2 Correlation Between Dynamic RDSon Transients and Carbon Related Buffer Traps in AlGaN/GaN HEMTs

CD-3 Investigation of Trapping Effects on AlGaN/GaN HEMT under DC Accelerated Life Testing

CD-4 Evaluations of Threshold Voltage Stability on COTS SiC DMOSFETs Using Fast Measurements

CD-5 Device Breakdown Optimization of Al2O3/GaN MISFETs

Design for Circuit Reliability

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CR-1 The Impact of Process Variation and Stochastic Aging in Nanoscale VLSI

CR-2 Mismatch Circuit Aging Modeling and Simulations for Robust Product Design and Pre-/Post-Silicon Verification

CR-3 Aging of IO Overdrive Circuit in FinFET Technology and Strategy for Design Optimization

CR-4 Robustness of Timing in-situ Monitors for AVS Management

Dielectric Reliability (Front-end and Back-end)

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DI-1 Moisture Impact on Dielectric Reliability in Low-k Dielectric Materials

DI-2 Impact of Trap Creation at SiO2/Poly-Si Interface on Ultra-thin SiO2 Reliability

DI-3 A Fast Reliability Screening Technique for Identification of Trap Generation

DI-4 Correlation between the Variation in the Initial Current at Stress and the Variation in the Failure Time During TDDB Testing of BEOL Structures

DI-5 Towards an Appropriate Accelerate Model for BEOL TDDB

DI-6 Evaluation of Inter and Intra Level TDDB of Cu/Low-k Interconnect for High Voltage Application

DI-7 Effect of H2O on TDDB for a Range of ULK ILD Materials with Varying Damage Resistance for Robust and Weak Liners

DI-8 Reliability-Performance Trade-off For Work- Function Optimization In Advanced Node Replacement Metal Gate Technology

ESD and Latch-up

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EL-1 ESD Self-Protection Design on 2.4-GHz T/R Switch for RF Application in CMOS Process

EL-2 Failure Mechanism of High-Voltage Isolated Lateral Diffused NMOS under High-Current Events

EL-3 Optimization of PESD Implant Design for ESD Robustness of 5V Drain-Back N-LDMOSFET

EL-4 On-Chip Protection in Precision Integrated Circuits Operating at High Voltage and High Temperature

EL-5 Improving the Long Pulse Width Failure Current of NPN in BiCMOS Technology

EL-6 Analysis of ESD Effects on Organic Thin-Film-Transistors by Means of TLP Technique

EL-7 Unique ESD Behavior and Failure Modes of AlGaN/GaN HEMTs

EL-8 New Insights on the ESD Behavior and Failure Mechanism of Multi Wall CNTs

System Reliability

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ES-1 Long-Term Reliability of a Hard-Switched Boost Power Processing Unit utilizing SiC Power MOSFETs

Failure Analysis

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FA-1 Dynamic Avalanche in Charge-Compensation MOSFETs Analyzed with the Novel Single Pulse EMMI-TLP Method

FA-2 Fast 3D Electro-Optical Frequency Mapping and Probing in Frequency Domain

FA-3 Direct Photo Emission Monitoring for High Power IGBT during Avalanche Operation

Interconnect Metallization Reliability

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IT-1 Optimizing Cu Barrier Thickness for Interconnects Performance, Reliability and Yield

IT-2 Semi-empirical Interconnect Resistance Model for Advanced Technology Nodes: A Model Apt for Materials Selection Based upon Test Line Resistance Measurements

IT-3 Electromigration: Multiphysics Model and Experimental Calibration


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MY-1 The Complete Time/Temperature Dependence of I-V drift in PCM Devices

MY-2 Reliability-Performance Tradeoff between 2.5D and 3D-Stacked DRAM Processors

MY- 3 Root Cause of Degradation in Novel HfO2-based Ferroelectric Memories

MY- 4 Voltage Acceleration and Pulse Dependence of Barrier Breakdown in MgO Based Magnetic Tunnel Junctions

MY-5 A Compact Model for RRAM Including Random Telegraph Noise

MY-6 System-Level Error Correction by Read-Disturb Error Model of 1Xnm TLC NAND Flash Memory for Read-Intensive Enterprise Solid-State Drives (SSDs)

MY-7 On the Variability of Threshold Voltage Window in Gate-Injection Versatile Memories with Sub-60mV/dec Subthreshold Swing and 1012-Cycling Endurance

MY-8 Random Telegraph Noise in HfOx Resistive Random Access Memory: from Physics to Compact Modeling

Packaging and 3D Assembly

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PA-1 Optimum Filler Geometry for Suppression of Moisture Diffusion in Molding Compounds

PA-2 A Finite Element Method Study of Delamination at the Interface of the TSV Interconnects

PA-3 Electromigration Induced Thermomigration in Microbumps by Thermal Cross-talk Across Neighboring Chip in 2.5D IC

Process Integration

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PI-1 Resolution of Poly Gate to Substrate Contact Short Reliability Failures on Non-Volatile Memory

PI-2 Highly-Accelerated WLR Learning Cycles for Development of a Trench MOSFET: Method and Case Study

Product IC Reliability

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PR-1 Modelling of 1T-NOR Flash Operations for Consumption Optimization and Reliability Investigation

PR-2 Near Neighbor Sort Yield & Wafer Sort Yield Impact on Product Burn-In and a Time-Dependent Reliability Study

PR-3 Machine Learning-Based Proactive Data Retention Error Screening in 1Xnm TLC NAND Flash

Photovoltaics Reliability

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PV-1 Study of the Potential-Induced Degradation Kinetics

PV-2 Potential Induced Degradation in High-Efficiency Bifacial Solar Cells

PV-3 Improvement of DSSC Performance by Voltage Stress Application

PV-4 Adhesion Requirements for Photovoltaic Modules of Polymeric Encapsulation

Soft Errors

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SE-1 Alpha-Particle and Neutron-Induced Single-Event Transient Measurements in Subthreshold Circuits

SE-2 Error Characterization and Mitigation for 16nm MLC NAND Flash Memory under Total Ionizing Dose Effect

SE-3 Investigating the Single-Event-Transient Sensitivity of 65 nm Clock Trees with Heavy Ion Irradiation and Monte-Carlo Simulation

SE-4 Exploiting Low Power Circuit Topologies for Soft Error Mitigation

SE-5 Estimation of Single-Event Transient Pulse Characteristics for Predictive Analysis

SE-6 Predicting the Vulnerability of Memories to Muon-Induced SEUs with Low-Energy Proton Tests Informed by Monte-Carlo Simulations

Transistor Reliability

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XT-1 Alteration of Oxide-Trap Switching Activity at Operating Condition By Voltage-Accelerated Stressing

XT-2 Nano-Scale Evidence for the Superior Reliability of SiGe High-k pMOSFETs

XT-3 Negative Bias Temperature Instability Lifetime Prediction: Considering Frequency, Voltage and Activation Energy via Novel Methodology of MSM-SFMF

XT-4 Device-Level Jitter as a Probe of Ultrafast Traps in High-k MOSFETs

XT-5 Spatio-Temporal Mapping of Device Temperature due to Self-Heating in Sub-22nm Transistors

XT-6 Surface-Potential-Based Compact Modeling of BTI

XT-7 Width and Layout Dependence of HC and PBTI Induced Degradation in HKMG nMOS Transistors

XT-8 Characterization and Modeling of NBTI Permanent and Recoverable Components Variability

XT-9 Temperature Sense Effect in HCI Self-heating de convolution – Application to 28nm FDSOI

XT-10 Comparative Experimental Analysis of Time-dependent Variability using a Transistor Test Array


Session 6A – ESD and Latch-up

Session Co-Chairs: Dimitri Linten, imec, Teruo Suzuki, Socionext
Section D

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8:30 a.m. – Session Introduction

8:35 a.m. – 6A.1 FinFET SCR Structure Optimization for High-Speed Serial Links ESD Protection

9:00 a.m. – 6A.2 Interposer FPGA with Self-protecting ESD Design for Inter-die Interfaces and its CDM Specification

9:25 a.m. – 6A.3 Investigation of Reverse Recovery Effects on the SOA of Integrated High Frequency Power Transistors

Break – 9:50 a.m.

10:20 a.m. – 6A.4 Modeling Feedback Effects in Metal Under ESD Stress

10:45 a.m. – 6A.5 Latchup Holding Voltages and Trigger Currents in a SOI Technology, G. Quax, T. Smedes, *NXP Semiconductors

11:10 a.m. – 6A.6 Experimental Study of Supply Voltage Stability during ESD (Late News)

Session 6B – 3D Assembly

Session Co-Chairs: Chandrasekara Kothandaraman, IBM, Kangwook Lee, Tohoku University
Section E

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8:30 a.m. – Session Introduction

8:35 a.m. – 6B.1 Impact of Local Stress in 3D Stacking Process on Memory Retention Characteristics in Thinned DRAM Chip

9:00 a.m. – 6B.2 Impact of Wafer Thinning on Front-end Reliability for 3D Integration

9:25 a.m. – 6B.3 Triangular Voltage Sweep (TVS) Characterisation for Through-Silicon-Via (TSV) Reliability

Break – 9:50 a.m.

10:20 a.m. – 6B.4 The Projection of the Incidence of Dielectric Cracking During Chip Joining with Lead Free Solder Bumps

10:45 a.m. – 6B.5 Key Metrics for the Electromigration Performance for Solder and Copper-based Package significant

11:10 a.m. – 6B.6 The State of Pb-free Solder – A Joint Reliability Overview (Late News)

Session 6C – Memory

Session Co-Chairs: Robin Degraeve, imec, Christian Monzio Compagnoni, Polytechnico di Milano
Section F/G

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8:30 a.m. – Session Introduction

8:35 a.m. – 6C.1 Quantitative Model for Post-program Instabilities in Filamentary RRAM

9:00 a.m. – 6C.2 Extensive Reliability Investigation of a-VMCO Nonfilamentary RRAM: Relaxation, Retention and Key

9:25 a.m. – 6C.3 A Step Ahead Toward a New Microscopic Picture for Charge Trapping/detrapping in Flash Memories

Break – 9:50 a.m.

10:20 a.m. – 6C.4 Channel and Near Channel Defects Characterization in Vertical InxGa1-xAs High Mobility Channels for Future 3D NAND Memory

10:45 a.m. – 6C.5 Data-Retention Time Prediction of Long-term Archive SSD with Flexible-nLC NAND Flash

11:10 a.m. – 6C.6 Data Archiving in 1x-nm NAND Flash Memories: Enabling Long-Term Storage using Rank Modulation and Scrubbing

Session 7A – Dielectric Reliability (Front-end and Back-end)

Session Co-Chairs: Ernest Wu, IBM, Bonnie Weir, Avago
Section D

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1:25 p.m. – Session Introduction

1:30 p.m. – 7A.1 The Physical Mechanism Investigation between HK/IL Gate Stack Breakdown and Time-dependent

1:55 p.m. – 7A.2 Multiphysics based 3D Percolation Framework Model for Multi-Stage Degradation and Breakdown in High-κ / Interfacial Layer Stacks

2:20 p.m. – 7A.3 Layout Dependence of Gate Dielectric TDDB in HKMG FinFET Technology

2:45 p.m. – 7A.4 CAFM Based Spectroscopy of Stress-Induced Defects in HfO2 with Experimental Evidence of the Clustering Model and Metastable Vacancy Defect State

Session 7B – Failure Analysis

Session Chair: Abdullah Yassine, AMD
Section E

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1:25 p.m. – Session Introduction

1:30 p.m. – 7B.1 Spontaneous Photon Emission from 32 nm and 14 nm SOI FETs

1:55 p.m. – 7B.2 Dynamical Observation of H-induced Gate Dielectric Degradation through Improved Nuclear Reaction Analysis System

2:20 p.m. – 7B.3 Transient Thermometry and HRTEM Analysis of RRAM Thermal Dynamics during Switching and Failure

2:45 p.m. – 7B.4 NVM Cell Degradation Induced by Femtosecond Laser Backside Irradiation for Reliability Tests

Session 7C – Product IC Reliability

Session Co-Chairs: Jerry Lee, Cisco, Brian Pedersen, Intel
Section F/G

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1:25 p.m. – Session Introduction

1:30 p.m. – 7C.1 BTI Induced Dispersion: Challenges and Opportunities for SRAM Bit Cell Optimization

1:55 p.m. – 7C.2 Aging-aware Adaptive Voltage Scaling of Product Blocks in 28nm Nodes

2:20 p.m. – 7C.3 Scenario-based Set-level HTOL Test (ASH III) for Product Quality and Reliability Qualifications on High-Speed Aps

2:45 p.m. – 7C.4 Reliability Characterizations of Display Driver IC on High-k / Metal-Gate Technology