Abstract Highlights

Each title links to a pdf with a description of the paper.

Tuesday, 11:15 a.m..
2A.2      Hot Carrier Reliability Characterization in Consideration of Self-Heating in FinFET Technology, M. Jin, C. Liu, S. Pae, Samsung

Tuesday, 3:15 p.m.
3A.4      A New Aspect of Time-dependent Clustering Model for Non-uniform Dielectric TDDB, T. Shimizu, Renesas Electronics Corporation

Tuesday, 3:15 p.m.
3B.4      Investigation of Logic Circuit Soft Error Rate (SER) in 14nm FinFET Technology, T. Uemura, S. Lee, S. Pae, J. Park, Samsung Electronics

Tuesday, 4:10 p.m.
3B.5      Bidirectional NPN ESD Protection in Silicon Photonics Technology, R. Boschke, S.-H. Chen*, M. Scholz*, G. Hellings*, P. Verheyen*, J. Van Campenhout**, D. Linten*, G. Groeseneken, KU Leuven, *IMEC, **Ghent University-IMEC

Tuesday, 4:35 p.m.
3B.6      Systematic Transient Characterization of Graphene Interconnects for on-Chip ESD Protection, Qi Chen*, Rui Ma, Fei Lu, Chenkun Wang, Ming Liu and Albert Wang, University of California, Riverside

Wednesday, 8:35 a.m.
4A.1      Negative-Bias Temperature Instability of GaN MOSFETs, Alex Guo and Jesús A. del Alamo, Massachusetts Institute of Technology

Wednesday, 8:35 a.m.
4C.1      Timing Characterizations of Device and CPU-like Circuit to Ensure Process Reliability, M.-H. Hsieh, TSMC

Wednesday, 2:00 p.m.
5A.1      Reliability of Single-LayerMoS2 Field-Effect Transistors with SiO2 and hBN Gate Insulators, Yu.Yu. Illarionov*,+, M. Waltl*, M.M. Furchi*, T. Mueller* and T. Grasser* *TU Wien, Austria +Ioffe Physical-Technical Institute, Russia

Wednesday, 2:25 p.m.
5B.2      Multi-Segment Electromigration Failure Mechanism in Cu/Low-k Dual Damascene Interconnects, M.-H. Lin, A. Oates, TSMC

Wednesday, 2:00 p.m.
5C.1      Muon-Induced Soft Errors in 16-nm NAND Flash Memories, M.Bagatin, S. Gerardin, A. Paccagnella, A. Visconti, S. Beltrami, M> Bertuccio, K. Ishida, C. Frost, A. Hillier, V. Ferlet-Cavrois, University of Padova, Micron TEchnology, RIKEN Nishina Center, Rutherford Apppleton Laboratory, ESA ESTEC, TEC-QEC

Thursday, 1:30 p.m.
7A.1      The Physical Mechanism Investigation between HK/IL Gate Stack Breakdown and Time-dependent Oxygen Vacancy Trap Generation in FinFET Devices, C. H. Yang, S. C. Chen, Y. S. Tsai, R. Lu, Y.-H. Lee,TQRD, TSMC