Product IC Reliability
Product IC Reliability
PR-1 Modelling of 1T-NOR Flash Operations for Consumption Optimization and Reliability Investigation
J. Coignus, G. Torrente*, A. Vernhet, S. Renard*, D. Roy*, G. Reimbold, CEA, LETI, *STMicroelectronics
Based on novel experimental capabilities, Flash NOR memory consumption, scalability and reliability trade-off is addressed, by mean of programming and erase operation schemes modelling. A fine tuning of programming energy and max. current is provided, together with an extended description of Flash programming dynamics along device ageing. Optimized cycling conditions are shown to reduce power consumption without any detrimental impact on device reliability.
PR-2 Near Neighbor Sort Yield & Wafer Sort Yield Impact on Product Burn-In and a Time-Dependent Reliability Study
R. Heller, Jr., Advanced Micro Devices
Local Yield is the yield of near neighbor die to a central die at wafer sort (excluding the results of the central die). It has been shown in literature that the local yield of a die can estimate the future reliability of the die. Die that come
from regions of other passing die pose less reliability risks than faulty regions. This is due to defect clustering and the fact that same killer defects that cause sort fails are the same types of defects that cause latent defects only differing in size and location. Based on information we can gather at Wafer Sort, does it make sense to have a “one size fits all” approach for a downstream production burn-in screen? What techniques can we use to better identify potentially unreliable die? Can we use Local Yield and Wafer Sort Yield to better determine burn-in durations? This paper examines all of these questions and the relationship between yield and reliability using both Local Yield and Wafer Sort Yield and production burn-in using a production dataset of AMD CPU. This paper also examines the time-dependent reliability fallout during production burn-in by near neighbor sort bin.
PR-3 Machine Learning-Based Proactive Data Retention Error Screening in 1Xnm TLC NAND Flash
Y. Nakamura, T. Iwasaki, K. Takeuchi, Chuo University
A screening method to proactively reduce data retention error, based on screening of PD-weak cells, where PD-weak cells have high program disturb error frequency. Repeated measurement of program disturb (P.D.), indicates that 25% of P.D. errors are concentrated in 3.5% of the memory cells, called PD-weak cells. PD-weak cells have 4× worse data retention (D.R.) than non- PD-weak cells, therefore retention errors can be reduced by PD-weak cell screening. Proactive D.R. detection is a new capability, because conventional retention testing times are not practical during product test. In 1Xnm TLC NAND flash, removal of PD-weak cells with <2% overhead extends D.R. by 30%. The method to measure PD-weak cells is described, as well as machine learning to model and detect PD-weak cells. Finally, detection rate vs. false detection cost is compared for 3 learning algorithms.