IRPS

Process Integration

Process Integration

PI-1 Resolution of Poly Gate to Substrate Contact Short Reliability Failures on Non-Volatile Memory

S. Chandrasekaran, P. Jowett, T. Mishra, C. Shafer, R. Cruz, K. Noronha, S. Bhosle, V. R. Sanivarapu, N. Rangaraju*, D. Kapoor*, Intel Micron Flash Technologies LLC, *Intel Corporation

Due to continual scaling of CMOS device dimensions, the dielectric spacing between poly gate (PG) and contact to substrate (Con) has been drastically reduced. This reduction in gate to substrate contact spacing has challenged the dielectric breakdown between poly gate and substrate contact. Several studies involving the breakdown of dielectric between gate and substrate contact have been reported in the past. In this paper, we report the elimination of poly gate to substrate contact shorts on 90 nm Non-Volatile Memory technology with the help of process optimizations in pre-metal dielectric stack. This led to a significant improvement in wafer level reliability metric to the tune of ~1.7X.

PI-2 Highly-Accelerated WLR Learning Cycles for Development of a Trench MOSFET: Method and Case Study

G. Hall, D. Moore, P. Burke, M. Suzuki, ON Semiconductor

ON Semiconductor Trench MOSFET integration process is designed to be manufacturable with high yields and world-class reliability. Power MOSFET discrete devices are required to pass a number of packaged level reliability (PLR) tests based on IEC guidelines [1], which involve very long time horizons -e.g. High Temperature Gate Bias (HTGB), and Reverse Bias (HTRB) have 1000+ hour time-on-test. When developing a new integration or design, it is of high value to have an expedient methodology for providing fast results on design-of-experiments (DOE), which lead to process or design paths with a high likelihood of passing qualification. In this study we describe the use of WLR methodology to identify an optimized Trench MOSFET gate salicidation scheme. The DOE splits were evaluated using a highly accelerated wafer level bias temperature instability test (WLBTI), and Wafer Level Time Dependent Dielectric Breakdown (WLTDDB). The process conditions which had acceleration factors predicting optimal results at PLR and use conditions were selected for qualification using the standard PLR program. The business case for using WLR methodology to evaluate cycles of learning is clear when one considers the impact to time-to-market of innovative technologies.