IRPS

Memory

Memory

MY-1 The Complete Time/Temperature Dependence of I-V drift in PCM Devices

M. Le Gallo, A. Sebastian, D. Krebs, M. Stanisavljevic, E. Eleftheriou, IBM Research – Zurich

Phase-change memory (PCM) devices are expected to play a key role in future computing systems as both memory and computing elements. Hence, a comprehensive understanding of the change in the current/voltage (I-V) characteristics of these devices with time and temperature is of considerable importance. Here, we present a unified drift model to predict the I-V characteristics at any instance in time and at any temperature. The model was validated on large sets of experimental data for an extensive range of time (10 orders of magnitude) and temperatures (180 – 400 K), different phase-change materials and a collection of 4k cells from a PCM chip.

MY-2 Reliability-Performance Tradeoff between 2.5D and 3D-Stacked DRAM Processors

S.M Hassan, W. Song, S. Mukopadhyay, S. Yalamanchili, Georgia Institute of Technology

MY-3 Root cause of degradation in novel HfO2-based Ferroelectric Memories M. Pešić, F. Fengler, S. Slesazeck, U. Schröder, T. Mikolajick, L. Larcher*, A. Padovani*, NaMLab gGmbH, *University of Modena and Reggio Emilia Summary:HfO2-based ferroelectrics reveal full scalability and CMOS integrability compared to perovskite-based ferroelectrics that are currently used in non-volatile ferroelectric random access memories (FeRAMs). Up to now, the mechanisms responsible for the decrease of the memory window have not been revealed. Thus, the main scope of this study is an identification of the root cause for the endurance degradation. Utilizing trap density spectroscopy for examining defect evolution with cycling of the device studied together with modeling of the degradation resulted in an understanding of the main mechanisms responsible for degradation of the ferroelectric behavior.

MY- 3 Root Cause of Degradation in Novel HfO2-based Ferroelectric Memories

Milan Pešić, Franz P. G. Fengler, Stefan Slesazeck, Uwe Schroeder, Thomas Mikolajick*
NaMLab gGmbH

HfO2-based ferroelectrics reveal full scalability and CMOS integratability compared to perovskite-based ferroelectrics that are currently used in non-volatile ferroelectric random access memories (FeRAMs). Up to now, the mechanisms responsible for the decrease of the memory window have not been revealed. Thus, the main scope of this study is an identification of the root causes for the endurance degradation. Utilizing trap density spectroscopy for examining defect evolution with cycling of the device studied together with modeling of the degradation resulted in an understanding of the main mechanisms responsible for degradation of the ferroelectric behavior.

MY- 4 Voltage Acceleration and Pulse Dependence of Barrier Breakdown in MgO Based Magnetic Tunnel Junctions

S. Van Beek, K. Martens, P. Roussel, G. Donadio, J. Swerts, S. Mertens, A. Thean, G. Kar, A. Furnemont*, G. Groeseneken, KU Leuven, *IMEC

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising non-volatile memory for high speed applications. The Magnetic Tunnel Junction (MTJ), the key element, contains a thin crystalline MgO dielectric
sandwiched in between two ferromagnetic layers. One of these magnetic layers retains a magnetic memory state, that can be altered by nanosecond current pulses. The nanometer thin MgO dielectric should show sufficient reliability at used switching voltages. For DRAM applications 1000FIT is required. The lifetime prediction is largely influenced by a voltage acceleration model. For MgO there is no consensus about this acceleration model however. Moreover, large dependencies on pulse width and duty cycle are reported. In this paper we study barrier breakdown time over a range of 11 orders of magnitude. With a maximum likelihood ratio method, we test the statistical significance of fits for different voltage acceleration models on 855 devices. We find that the power law best describes voltage acceleration with a p-value less than 1e-10. In addition we observe no significant influence of duty cycle (1% – 77%) and pulse widths (10ns – 1us) down to 30ns.

MY-5 A Compact Model for RRAM Including Random Telegraph Noise

B.Guan, J. Li*, Sun Yat-sen University, *University of Wisconsin

Read instability in resistive random access memory (RRAM) devices, mainly caused by random telegraph noise (RTN), needs to be fully addressed before its wide commercial adoption. To fulfill the increasing need for circuit level reliability study, it is desirable to develop a compact model to account for RTN effect. In prior art, several analytical
compact models have been developed to simulate resistive switching behavior . However, none of them are capable of capturing current fluctuation caused by RTN. In this paper, we develop a RRAM compact model for circuit simulation, which for the first time takes into account the RTN effect. The model is validated using different sets of experimental data. Our simulation fits well with measurements both in high resistance state (HRS) and low resistance state (LRS).

MY-6 System-Level Error Correction by Read-Disturb Error Model of 1Xnm TLC NAND Flash Memory for Read-Intensive Enterprise Solid-State Drives (SSDs)

Y. Deguchi, T. Tokutomi, K. Takeuchi, Chuo University

Read-disturb Modeled LDPC (RDM-LDPC) ECC is proposed. Conventional Advanced Error-Prediction LDPC (AEP-LDPC) corrects data-retention errors of data-storage-purpose SSDs storing photos, movies, etc. but cannot correct read-disturb errors. For read-intensive computing-purpose enterprise SSDs, this paper analyzes the read-disturb errors, develops the error model of 1Xnm TLC NAND Flash memory and proposes ECC suitable for read-disturb errors. It is experimentally demonstrated that proposed RDM-LDPC extends the read cycle of SSDs by 5000-times.

MY-7 On the Variability of Threshold Voltage Window in Gate-Injection Versatile Memories with Sub-60mV/dec Subthreshold Swing and 1012-Cycling Endurance

Y. Chiu, C. Cheng*, M.-H. Lee, C. Liu*, P.-W. Chen*, P.-C. Chen*, C. Chang, S.Yen, C. Fan, H. Hsu, G. Liou*, C. Chang, C. Liu*, W.-C. Chou*, National Chiao Tung University, *National Taiwan Normal University

Incorporating a charge-trapped ZrSiO with ferroelectric HfZrO dielectrics, we demonstrated a gate-injection versatile memory with sub-60mV/dec subthreshold swing (SS) and large threshold voltage window (ΔVT) of >2V under a fast 20-ns speed. Moreover, it is revealed that the local defects at ZrSiO/HfZrO interface affect the ferroelectric negative capacitance tuning and thus increases the variability of VT and SS during 1E12 cycling endurance.

MY-8 Random Telegraph Noise in HfOx Resistive Random Access Memory: from Physics to Compact Modeling

F.M. Puglisi, L. Larcher, P. Pavan, University of Modena and Reggio Emilia

As RRAM technology is entering the industrial phase, compact models accounting for variability and RTN effects at circuit level are essential to evaluate the technology potential. Variability and RTN represent major concerns for HfOx RRAM applications such as non-volatile memory, neuromorphic computing, and Physical Unclonable Function (PUF). In this paper, starting from the physics of charge transport and RTN, we develop a physics-based compact model for RTN in RRAM, valid in both high-(HRS) and low-resistance state (LRS). The proposed model is validated on a wide data set and well reproduces also data from the literature. The RTN model can be easily integrated in compact RRAM device models and can describe I-time traces in both resistive states.