Interconnect Metallization Reliability

Interconnect Metallization Reliability

IT-1 Optimizing Cu Barrier Thickness for Interconnects Performance, Reliability and Yield

T. Shen, B. Rajagopalan, M.C. Silvestre, E. Ramanathan, A.S Mahalingham, W. Zhang, K.B. Yeap, P. Justison, Globalfoundries

Cu barrier thickness optimization on our 90nm pitch Vx/Mx layers with porous ULK SiCOH (κ=2.55) was systematically investigated. Both via resistance and intrinsic EM performance favors thinner TaN and Ta films, however, the robustness of the plating requires thicker Ta to improve seed quality that withstand dissolution during plating. Overall, a thin TaN barrier with moderate thick Ta provides the optimum solution for performance, reliability and yield.

IT-2 Semi-empirical Interconnect Resistance Model for Advanced Technology Nodes: A Model Apt for Materials Selection Based upon Test Line Resistance Measurements

P. Roussel, I. Ciofi, R. Degraeve, V. Vega, N. Jourdan, R. Baert, D. Linten, J. Bömmels, Z. Tőkei, G. Groeseneken*, A. Thean, IMEC, *KU Leuven

As the dimensions of interconnects shrink into the nanoscale for the NX node, their electrical conductivity becomes dependent on their size, even at room temperature. This paper presents a semi-empirical interconnect resistance model apt for fitting wire resistance data. The model combines grain boundary and sidewall scattering effects with the impact of Line Edge Roughness (LER). It allows subsequent selection of interconnect metallization material candidates through extrapolation to target widths of future technology nodes on the basis of their wire resistance, while still considering other performance metrics like yield, electromigration and TDDB. A refined model parameter calibration procedure, that accounts for interconnect height and width variability between the test structures is demonstrated for two Cu metallization schemes, employing Co and Ru as a metal liner, respectively. The model allows inclusion of more accurate, geometry dependent interconnect resistance estimators in higher abstraction level simulators, enabling a more realistic assessment of the impact of BEOL parasitics on circuit delay at advanced technology nodes.

IT-3 Electromigration: Multiphysics Model and Experimental Calibration

G. Marti, W.H. Zisser, L. Arnaud*, Y. Wouters**, STMicroelectronics, *CEA-Leti Minatec, **SIMAP, ***Technische Universität Wien

Electromigration (EM) is one of the main reliability failure mechanism of integrated circuit interconnects. The result of EM in copper interconnects is void nucleation and growth close to the cathode. For EM tests, most commonly elementary structures are stressed under accelerated conditions (high current and temperature) until degradation occurs. The understanding of the main mechanism governing the reliability of copper interconnects is mandatory to develop lifetime predictive laws and allows architecture optimizations of future MOS technologies. Thus more accurate and less pessimistic full-chip EM assessment and mean-time-to-failure (MTTF) prediction will require a development of new methods that deal with the design of the grid structure and take redundancy into account. We describe in this work a new methodology to calibrate an existing EM numerical model. The effective charge (Z*) of this technology has been extracted experimentally. Furthermore, the proposed post-processing method allowed us to find the critical tensile stress of void nucleation. This method allows to answer design requests about void nucleation
which may depend upon geometry and process conditions. Taking into account these parameters will increase the accuracy of reliability prediction at design level and help designers with high current density needs.