IRPS

ESD and Latch-up

ESD and Latch-up

EL-1 ESD Self-Protection Design on 2.4-GHz T/R Switch for RF Application in CMOS Process

C.-Y.Lin, R.-H. Liu*, M.-D. Ker*, National Taiwan Normal University, *National Chiao Tung University

The RF transceiver front-end for 2.4-GHz applications realized by a fully integrated T/R switch with ESD self-protection capability is presented in this work. Experimental results show that the proposed design can provide enough ESD self-protection capability with good RF performances.

EL-2 Failure Mechanism of High-Voltage Isolated Lateral Diffused NMOS under High-Current Events

C.-H. Wu, J.-H. Lee*, C.-H. Lien, National Tsing Hua University, *Globalfoundries

In this study, the mechanism of the effect of a high-voltage (HV) NWell guardring (NW-GR) on the electrostatic discharge (ESD) robustness of the HV isolated lateral diffused NMOS (HV ISO-LDNMOS) is investigated. The device fails on low-voltage ESD zapping events when the HVNW-GR is connected to the drain, whereas the device passes these events once it is floated.

EL-3 Optimization of PESD Implant Design for ESD Robustness of 5V Drain-Back N-LDMOSFET

C. Chiang, P.C. Chang, P.-S. Tseng, P.-Y. Lai, H. Tang, K.C. Su, UMC

An N-LDMOS ESD protection device with drain back and PESD optimization design is proposed. With PESD layer enclosing the N+ drain region, a parasitic SCR is created to achieve high ESD level. When PESD is close to gate, the turn-on efficiency can be further improved (Vt1: 11.2V reduced to 7.2V) by the punch-through path from N+/PESD to PW. The proposed ESD N-LDMOS can sustain over 8KV HBM with low trigger behavior.

EL-4 On-Chip Protection in Precision Integrated Circuits Operating at High Voltage and High Temperature

J. Salcedo, J.-J. Hajjar, J. Zhao, Analog Devices

A new high voltage swing bipolar ESD (electrostatic discharge) protection device for enabling low leakage precision mixed-signal interface circuits (ICs) operating at high voltage (~ 40V to 60V) and high temperature (~125ᵒC to 200ᵒC) is presented. Under these operating conditions, parasitic structures in junction-isolated high voltage process technologies induce unexpected shift in the leakage current over time, leading to malfunction in the precision high voltage input/output interface circuit. A proposed device design addresses the low leakage targets at the mentioned operating conditions, while achieving the required ESD robustness of the high voltage interface for industrial applications.

EL-5 Improving the Long Pulse Width Failure Current of NPN in BiCMOS Technology

Y. Xiu, A. Appaswamy, Z. Chen*, A. Salman, M. Dissegna, G. Boselli, E. Rosenbaum*, Texas Instruments, *University of Illinois at Urbana-Champaign

The pulse width dependency of the failure current for NPN structures in a 0.18-μm BiCMOS technology is studied using measurements and TCAD simulation. The desired “Wunsch-Bell” behavior is not observed due to formation of current filaments in this device; however, the failure current for long pulse widths can be increased by layout changes.

EL-6 Analysis of ESD Effects on Organic Thin-Film-Transistors by Means of TLP Technique

N. Wrachien, M. Barbato, A. Cester, A. Rizzo, G. Meneghesso, R. D’Alpaos*, G. Turatti*, G. Generali*, M. Muccini**, University of Padova, *ETC srl, **CNR-ISMN

We analyzed the effects of Electrostatic Discharge events on large area high voltage Organic Thin Film Transistors, using the transmission line pulsing technique. These transistors survived ESD events exceeding 500V. A partial dielectric breakdown occurred at voltage higher tan 600V. Small mobility and threshold voltage variations are observed, prior breakdown.

EL-7 Unique ESD Behavior and Failure Modes of AlGaN/GaN HEMTs

B. Shankar, M. Shrivastava, Indian Institute of Science

Present experimental study reports various failure modes under ESD stress conditions and distinct ESD behavior of AlGaN/GaN HEMTs for the first time. Effect of MESA isolation and gate finger on the ESD behavior of HEMTs is analyzed. Effect of pulse width on ESD robustness and trigger voltage is observed and a unique power law like behavior is found. Cumulative nature of device degradation under ESD stress condition is discovered. Correlation between depth of snapback and failure threshold with % device degradation is found. Finally, impact of inverse piezoelectric effect in AlGaN/GaN system, fringing electric field, role of contact resistivity, temperature and field induced contact metal migration and premature breakdown of parasitic MESA Schottky junction are studied in context to AlGaN/GaN HEMT failure ESD conditions.

EL-8 New Insights on the ESD Behavior and Failure Mechanism of Multi Wall CNTs

A. Mishra, M. Shrivastava, Indian Institute of Science

ESD conditions, through inner and outer shells of MWCNT is explored. ESD time scale current annealing behavior of outer and inner shells was discovered, which is unique to MWCNTs. Shells – by – shell failure was confirmed to be the universal failure mode of MWCNTs. Failure behaviors of suspended and collapsed (tubes resting on dielectric surface) tubes in single and bundled configuration are discussed.