Dielectric Reliability (Front-end and Back-end)

Dielectric Reliability (Front-end and Back-end)

DI-1 Moisture Impact on Dielectric Reliability in Low-k Dielectric Materials

K.-D. Lee, Q. Yuan, A. Patel, Z. Mai, L. Brown, S. English, Samsung Austin Semiconductor

With intentional moisture uptake and removal, we modulate the moisture level in porous low-k dielectric materials, and investigate the moisture impact on dielectric reliability at a wide range of stress conditions. From this study, we confirm moisture can cause a significant degradation in dielectric reliability (i.e., x1.0E-06 in TDDB lifetimes) . Interestingly, the moisture impact is not permanent (with good Cu-diffusion barrier) and can be restored effectively with a high temp annealing at ≥ 350°C. Different from previous studies, moisture does not always increase the leakage currents nor change the TDDB modeling parameters, indicating there are at least two moisture states in porous low-k dielectric materials. In this paper, we will discuss the moisture-induced reliability degradation mechanisms.

DI-2 Impact of Trap Creation at SiO2/Poly-Si Interface on Ultra-thin SiO2 Reliability

Y. Mitani, M. Suzuki, Y. Higashi, R. Takaishi, Toshiba Corporation

The relationship between TDDB characteristics of the devices having ultrathin SiO2 as gate dielectrics and the hydrogen-related trap creation have been re-investigated from the viewpoint of the oxidation process dependence. In order to study the influence of hydrogen on the reliability, deuterium isotope effect has been used. As a result, the Weibull distributions of time-to-breakdown (tBD) depends on the oxidation process condition even under the same oxidation temperature. Trap creation at gate oxide interface strongly correlates to the dielectric breakdown in ultra-thin gate oxides However, this oxidation process dependence could not be explained only by the amount of hydrogen release from SiO2/Si substrate interface From the experimental results of low-voltage SILC, it can be concluded that not only the released hydrogen from SiO2/Si substrate interface but also those from Poly-Si/SiO2 interface correlates to the breakdown mechanisms.

DI-3 A Fast Reliability Screening Technique for Identification of Trap Generation

K. Joshi, Z.-R. Xiao, S.-H. Gao, C. Huang, T.-M. Shen, P.J. Liao, Y.-H. Lee, J-R. Shih, Taiwan Semiconductor Manufacturing Company

SILC spectrum technique is used to identify trap generation location in both PMOSFETs and NMOSFETs under BTI stress. It is validated using SILC spectrum technique that BTI stress in PMOSFETs leads to trap generation in IL/HK intermix whereas in NMOSFETs leads to trap generation in HK layer. Atomistic simulations are further performed to calculate formation energy for oxygen vacancies in various gate oxide layers. It has been validated that it is easy to generate hole traps in IL/HK intermix region under NBTI stress in PMOSFETs and easy to generate electron traps in HK layer in NMOSFETs under PBTI stress. The advantage of this technique is its ease of use and higher throughput thus making it an ideal tool for a quick scanning of trap generation locations and to understand the reliability strength of each layer under different processing conditions.

DI-4 Correlation between the Variation in the Initial Current at Stress and the Variation in the Failure Time During TDDB Testing of BEOL Structures

R. Filippi, C. Christiansen, A. Kim*, B. Li*, P-C. Wang, Globalfoundires, *IBM

A novel approach for estimating variation in the TDDB failure time is reported. The results for various test structures reveal that variation in the initial current at stress reasonably predicts variation in the TDDB failure time. The approach is a non-destructive method that only requires a current measurement, making it an efficient monitor of the expected TDDB lifetime behavior during manufacturing of an established process.

DI-5 Towards an Appropriate Accelerate Model for BEOL TDDB

R. Muralidhar, E. Linger, T. Shaw**, A. Kim, G. Bonilla*, IBM TJ Watson Research Center

We have evaluated the veracity of BEOL acceleration models using the largest set of data spanning 3 pitches. The raw data indicates same acceleration trends in the 3 pitches enabling them to fall into a universal curve by re-normalization to account for different areas. While the Root-E (RE), Impact Damage and Power-Law (PL) models fit data over entire range well, it is seen that only the Impact Damage and Power Law models predict the low field data when high field data alone is used to fit the models. This ability to extrapolate and the constancy of acceleration factors at low and high fields makes these models more appropriate for determining lifetime at operating conditions from a fit of high field data alone. While the ID model has 3 parameters and presents fitting challenges, the PL model is a good practical alternative and may have its physical basis on arguments based on scaling theory. The paper will additionally discuss in detail statistical analysis including clustering model, fitting aspects of ID model and physical basis of the power-law model from scaling point of view.

DI-6 Evaluation of Inter and Intra Level TDDB of Cu/Low-k Interconnect for High Voltage Application

M. Lin, C. Yang, H.-Y. Chen, A. Juan, K.C. Su, United Microelectronics Corp.

The conduction current and TDDB of intra and two kinds of inter level low-k dielectric structures for high voltage application are studied. Electrical field distributions are different on the different structures and impact the TDDB results. Failure analysis shows the Cu ion diffusion and SiCN interface are the dominant impact factor of the low-k dielectric breakdown. An inter level layout design principle to improve dielectric reliability under high voltage operation is suggested.

DI-7 Effect of H2O on TDDB for a Range of ULK ILD Materials with Varying Damage Resistance for Robust and Weak Liners

E. Linger, R. Laibowitz*, T. Shaw, S. Cohen, A. Raja*, IBM TJ Watson Research Center, *Columbia University

In this study we look at the correlation between TDDB lifetime, in the presence of intentionally introduced H2O and top surface damage for different ILD materials using a robust liner. The activation energy for the movement of loosely bound physi-adsorbed H2O has been obtained using AC loss measurements. We also explore the role of moisture in drawing Cu out of metal lines through an intentionally fabricated thin/weak liner under prolonged stress at a relatively low voltage. AC loss, I-V, triangular voltage sweep (TVS) and TDDB measurements all provide evidence that Cu is migrating out of the lines into the ILD.

DI-8 Reliability-Performance Trade-off For Work- Function Optimization In Advanced Node Replacement Metal Gate Technology

R. Ranjan, T. Nigam, B. Parameshwaran, Y. Liu, S.F. Yap, Globalfoundries

In this work, we explore the complex interaction of the gate stack process and time-dependent-dielectric breakdown (TDDB) in high-K (HK) replacement metal gate (RMG) technology. TDDB is a key reliability metric governing the product lifetimes under long-term operation. Based on this study, it is observed that TDDB is greatly modulated by the proximity of Al to the MG/HK interface. The key parameter modulated by gate stack optimization is voltage acceleration exponent (VAE) for TDDB. All observations indicate higher VAEs can be achieved by keeping the Al away from the MG/HK interface.