IRPS

Design for Circuit Reliability

Design for Circuit Reliability

CR-1 The Impact of Process Variation and Stochastic Aging in Nanoscale VLSI

S. Kiamerh, P. Weckx*, M. Tehoori, B. Kaczer*, H. Kukner*, P. Raghavan*, G. Groeseneken**, F. Catthoor*, Karlsruhe Institute of Technology, *IMEC, **KU Leuven

With the down-scaling of CMOS technology into deep nano-scale era, negative-bias temperature instability (NBTI) effect becomes stochastic due to its widely distributed defect parameters. As a result, the delay degradation due to intrinsic variability of NBTI becomes also stochastic and the matter is aggravated when it is combined with process variation (PV). Accurate stochastic timing analysis of the circuit becomes very important in this case since over and under margining can lead to significant performance or yield loss (timing failure), respectively. This paper proposes a scalable flow and investigates the combined effect of stochastic NBTI and process variation on the performance of the VLSI design at the circuit level in a 7 nm FinFET technology node by abstracting atomistic NBTI models (for the stochastic behavior) to the circuit timing analysis flow.

CR-2 Mismatch Circuit Aging Modeling and Simulations for Robust Product Design and Pre-/Post-Silicon Verification

H. Shim, Y. Kim, J. Jeon, Y. Cho, J. Park, S. Pae, H. Lee, Samsung Electronics

As technology scales down, PMOS NBTI-induced mismatch, in addition to the NBTI mean-shifts and time0-Vt variation, is critical for designing circuitry having matched pair transistors, such as OP amplifier. This paper covers mismatch aging models incorporated into design simulation tool for PMIC products and used the Monte-Carlo simulation to consider process and systematic variations for robust design. Circuit simulation for PMIC OP Amp and its output characteristics were investigated and then further validated through the post-silicon HTOL stress. The pre-silicon simulation further enables to optimize HTOL stress conditions.

CR-3 Aging of IO Overdrive Circuit in FinFET Technology and Strategy for Design Optimization

S.-E. Liu, M.-H. Yu, Y.-J. Chen, J.-Y. Jao, M.-Z. Lin, Y.-H. Fang, M.-J. Lin, MediaTek

We investigated aging property of FinFET-based I/O overdrive circuits (IP) and proposed design strategies of optimization among performance/area/reliability. Aging behavior of I/O overdrive IP with 16nm FinFET process has been extracted and compared with 20nm planar-transistor process. Both pulldown and pull-up driving degradation are worse in the FinFET than planar IP. An aging simulation framework was built from transistor-level aging databases and further calibrated by an empirical equation and IP-level measurements. Finally, a design guideline was discussed and proposed to pursue balance of performance/ area/reliability, which is thus improved 13%/8%/37% respectively in our optimized design.

CR-4 Robustness of Timing in-situ Monitors for AVS Management

A. Benhassain, F. Cacho, V. Huard, S. Mhira, L. Anghel*, C. Parthasarathy, A. Jain, A. Sivadasan, STMicroelectronics, *Grenoble University

This paper deals with the fundamental aspects of the introduction of aging sensor in digital circuit, describing a new In-situ Timing Monitor (ISM), insertion flow and experimental results .