CD-1 On Conduction Mechanisms through SiN/AlGaN based Gate Dielectric and Assessment of Intrinsic Reliability
A. Banerjee, P. Vanmeerbeek, L. De Schepper, S. Vandeweghe, P. Coppens, P. Moens, ON Semiconductor
The first section of this article focuses on the investigations of the gate leakage conduction mechanisms under forward and reverse bias conditions using temperature dependent Jg-Eg characteristics on a Silicon Nitride (SiN)/AlGaN based Metal-Insulator-Semiconductor (MIS) structure. TCAD study under forward bias conduction show majority of the voltage drop on the SiN layer only. The model fitting the electrical characteristics was observed to be Poole- Frenkel (PF) emission. Under reverse bias condition, the entire voltage drop occurs on the entire SiN/AlGaN/GaN. The conduction mechanism responsible for the leakage was found to be Fowler-Nordheim (FN) tunneling along with a thermionic emission component. Second section of this article focuses on the Time Dependent Dielectric Breakdown (TDDB) measurements and lifetime extrapolation of the SiN/AlGaN based di-electric stack. TDDB measurements were done under constant field stress for different temperatures. Normalization of the data exhibited only field accelerated degradation with no influence from the temperature.
CD-2 Correlation Between Dynamic RDSon Transients and Carbon Related Buffer Traps in AlGaN/GaN HEMTs
F. Iucolano, A. Parisi, S. Reina, A. Patti, S. Coffa, G. Meneghesso*, G. Verzellesi**, F. Fantini**, A. Chini**, STMicroelectronics, *University of Padova, **University of Modena and Reggio Emilia
The on resistance increment observed when the device is operated at high drain-source voltages is one the topics that limits the performance of the AlGaN/GaN HEMT devices. In this paper, the physical mechanisms responsible of the RDSon degradation are investigated. The dynamic RDSon transient method is used in order to get insight to characterize the traps states. By calculating the Arrhenius plot associated with the RDSon transients an activation energy of 0.86eV was extracted, that can be correlated to the traps due to the incorporation of Carbon inside the buffer. This hypothesis was further supported by the analyses performed on a simpler structure (TLM). By applying a negative substrate bias the effect of only the buffer traps was studied. A fairly close value of the activation energy (0.9eV) to the one extracted when analyzing the RDSon transient was obtained.
CD-3 Investigation of Trapping Effects on AlGaN/GaN HEMT under DC Accelerated Life Testing
W. Sun, C. Lee*, P. Saunier*, S. Ringel, A. Arehart, Ohio State University, *Qorvo Inc
GaN-based high electron mobility transistors (HEMTs) were subjected to DC-based accelerated life testing to determine which defect levels form or are activated, and how they impact the static and dynamic HEMT performance. The primary static changes were a negative shift of the threshold voltage and an increase in knee walkout/onresistance. The primary dynamic effect of the stressing appeared in the form of a time-dependent increase in the onresistance, and this was found to correlate to first order with formation and/or activation of traps at EC-0.57 and EC-0.72 eV traps that contributed to the dynamic changes, and the EC-1.5 eV trap was likely responsible for the static change in onresistance. Trapping kinetics analysis revealed that the physical sources for the EC-0.57 and EC-0.72 eV states are not simple, ideal, non-interacting point defects, but instead are associated with physically extended defects, such as dislocations, and/or defect complexes.
CD-4 Evaluations of Threshold Voltage Stability on COTS SiC DMOSFETs Using Fast Measurements
D. Habersat, R. Green, A. Lelis, US Army Research Laboratory
Threshold voltage (VT) stability of commercial SiC DMOSFETs during bias-temperature stressing was evaluated using the fast-ID and fast ID-VGS measurement techniques at both room and elevated temperatures. Unipolar bias stress results confirmed that there is a rapid recovery of VT and that all vendors’ devices showed the same basic charge-trapping behavior, although some differences were observed in negative bias response at high temperatures. In situ VT measurements during 10 kHz gate switching showed stable device operation at room temperature but accelerating VT drift and increasing switching oxide trap densities when operated at 175 °C. VT hysteresis during high temperature gate switching indicates the presence of a mobile ion or polarization effect in addition to the expected interface- and oxide-trap charging mechanisms.
CD-5 Device Breakdown Optimization of Al2O3/GaN MISFETs
X. Kang, S. Yamazaki, K. Takeuchi, Chuo University
In this paper we demonstrate a solution to achieve robust enhancement-mode Al2O3/GaN MISFETs with a high breakdown voltage and suggest a possible model for the device off-state breakdown. It is found that the device breakdown exhibits different gate voltage dependence for different surface treatments before the gate dielectric deposition. The device performance is greatly improved by using an in-situ surface plasma treatment. The improved device performance is explained by a reduction of traps at the Al2O3/GaN interface, which finally leads to a reduction in the amount of trapped positive charges and associated with that a reduction of the effective electric field across the gate dielectric when the device isin off-state. Several experimental results support this hypothesis: (1) The recoverable negative threshold voltage shift after reverse gate bias depends on the interface clean before gate dielectric deposition, (2) The reverse bias gate dielectric breakdown voltage is improved by this interface plasma treatment, although the forward bias gate dielectric breakdown voltage is identical.