Poster Session & Reception

2018 IRPS Poster Session and Reception

The poster session and reception will be held on March 14th (Wed.) 6:00 PM – 9:00 PM in the Atrium. During the reception, we will serve beverages, pizza, and cookies to welcome our attendees.

For poster authors, please follow the poster instructions (download) to prepare your work.  You need to ready your poster prior the conference and carefully carry it to the symposium. Each poster has a designated display board. The author should attach their poster between 5:45 pm – 6:00 pm on March 14th (Wed.) and stand by for poster session attendees to come.

3DOptimal Design of Dummy Ball Array in Wafer Level Package to Improve Board Level Thermal Cycle Reliability (BLR)Seongwon Jeong and Jinseok Kim
CRStudy of Impact of BTI's Local Layout Effect Including Recovery Effect on Various Standard-Cells in 10nm FinFETMitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Yasumasa Tsukamoto, Koji Shibutani and Koji Nii
CRA Multi-bits/cell PUF Using Analog Breakdown Positions in CMOSKai-Hsin Chuang, Erik Bury, Robin Degraeve, Ben Kaczer, Thomas Kallstenius, Guido Groeseneken, Dimitri Linten and Ingrid Verbauwhede
CRNew Insights into the HCI Degradation of Pass-gate Transistor in Advanced FinFET TechnologyPengpeng Ren, Changze Liu, Zhenghao Gan, Waisum Wong, Runsheng Wang and Ru Huang
CRDevice-level variability tolerance of a RRAM-based Self-Organizing Neuromorphic systemMarta Pedro, Javier Martin-Martinez, Enrique Miranda, Mireia B Gonzalez, Rosana Rodriguez, Francesca Campabadal and Montserrat Nafria
CRWeighted Time Lag Plot Defect Parameter Extraction and GPU-based BTI Modeling for BTI VariabilityVictor M. van Santen, Javier Diaz-Fortuny, Hussam Amrouch, Javier Martin-Martinez, Rosana Rodriguez, Rafael Castro-Lopez, Elisenda Roca, Francisco V. Fernandez, Jörg Henkel and Montserrat Nafria
ELA Case Study of ESD Trigger Circuit: Time-out and StabilityKuo-Hsuan Meng, Mohamed Moosa, Cynthia Torres and Jim Miller
FAA Research Study on Unsupervised Machine Learning Algorithms for Early Fault Detection in Predictive MaintenanceNagdev Amruthnath
GDNew insight on TDDB area scaling methodology of non-Poisson systemsTian Shen, Kong Boon Yeap, Sean Ogden, Cathryn Christiansen and Patrick Justison
GDReliability evaluation of defect accounted time-dependent dielectric breakdown with competing-mixture distributionShinji Yokogawa and Kazuki Tate
GDImpact of forming gas annealing on the degradation dynamics of Ge-Based MOS stacksFernando Aguirre, Sebastian Pazos, Felix Palumbo, Sivan Fadida, Roy Winter and Moshe Eizenberg
GDReliability of MgO in Magnetic Tunnel Junction formed by Sputtered MgO and Oxidation of MgAkinobu Teramoto, Jun-ichi Tsuchimoto, Mariko Hayashi, Hyeon-woo Park, Keiichi Hashimoto, Tomoyuki Suwa and Shigetoshi Sugawa
GDStudy of dynamic TDDB in scaled FinFET technologiesKustubh Joshi, S.W. Chang, D.S. Huang, P.J. Liao and Y.-H. Lee
GDDielectric breakdown in hexagonal boron nitride dielectric stacksXianhu Liang, Felix Palumbo, Yuanyuan Shi, Fei Hui, Bin Yuan, Xu Jing and Mario Lanza Martinez
GDOxide Breakdown Path as a Nanoscale Electro-Optical Switch/SensorYu Zhou, Diing Shenp Ang, Pranav Sairam Kalaga and Sankara Rao Gollu
GDHigh Voltage Time-Dependent Dielectric Breakdown in Stacked Intermetal DielectricsSangHoon Shin, Yen-Pu Chen, Woojin Ahn, Honglin Guo, Byron Williams, Jeff West, Tom Bonifield, Dhanoop Varghese, Srikanth Krishnan and Muhammad Ashraful Alam
GDMethod to assess the Impact of LER and Spacing Variation on BEOL Dielectric Reliability using 2D-Field Simulations for <20nm SpacingDeniz Kocaay, Philippe Roussel, Kristof Croes, Ivan Ciofi, Alicja Lesniewska and Ingrid De Wolf
MRElectromigration Failure Rate of Redundant ViaJae-Gyung Ahn, Ping-Chin Yeh and Jonathan Chang
MRModeling Self-Heating Effects in advanced CMOS nodesMelissa Arabi, Xavier Federspiel, Antoine Cros, Vincent Huard and Cheick Ndiaye
MYCorrelation between SET-State Current Level and Read-Disturb Failure Time in a Resistive Switching MemoryPo-Cheng Su, Chih-Wei Wang and Tahui Wang
MYSub-pJ Consumption and Short Latency Time in RRAM Arrays for High Endurance ApplicationsGilbert Sassine, Cecile Nail, Luc Tillie, Diego Alfaro Robayo, Alexandre Levisse, Carlo Cagli, Khalil El Hajjam, Jean Francois Nodin, Elisa Vianello, Mathieu Bernard, Gabriel Molas and Etienne Nowak
MYHigh-Temperature and High-Field Cycling Reliability of PZT Films Embedded within 130 nm CMOSGlen Walters, Paul Chojecki, Alexandra Garraud, Scott Summerfelt, John Rodriguez, Antonio Acosta and Toshikazu Nishida
MYSuppression of Endurance-stressed Data-retention Failures of 40nm TaOx-based ReRAMShouhei Fukuyama
MYRelaxing the STT-MRAM reliability challenge by scaling MgO thicknessB O'Sullivan, S VanBeek, P Roussel, S Rao, W Kim, S Couet, J Swerts, F Yasin, D Crotti, D Linten and G Kar
MYChip-Level Characterization and RTN-Induced Error Mitigation beyond 20nm Floating Gate Flash MemoryT. W. Lin, S.H. Ku, C.H. Cheng, C.W. Lee, Ijen Huang, Wen-Jer Tsai, T.C. Lu, W.P. Lu, K.C. Chen, Tahui Wang and Chih-Yuan Lu
MYCross Error Elimination ECC by Horizontal Error Detection and Vertical-LDPC ECC to Increase Data-Retention Time by 230% and Acceptable Bit-Error Rate by 90% for 3D-NAND Flash SSDsShun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Kyoji Mizoguchi and Ken Takeuchi
PIInvestigation of Monolayer MX2 as Sub-Nanometer Copper Diffusion BarriersKirby Smithe, Zhongwei Zhu, Connor Bailey, Eric Pop and Alex Yoon
PREvaluation on Flip-flop Physical Unclonable Functions in a 14/16-nm Bulk FinFET TechnologyHangfang Zhang, Hui Jiang, Madison Eaker, Kurt Lezon, Balaji Narasimham, Nihaar Mahatme, Lloyd Massengill and Bharat Bhuva
PVCharge State Evaluation of Passivation Layers for Silicon Solar Cells by Scanning Nonlinear Dielectric MicroscopyKento Kakikawa, Yuji Yamagishi, Katsuto Tanahashi, Hidetaka Takato and Yasuo Cho
PVPerformance Improvement of tandem amorphous / microcrystalline Si photovoltaic modules under changes in illumination conditionsFabio Ricco Galluzzo, Andrea Scuto, Cosimo Gerardi, Anna Battaglia, Andrea Canino, Francesco Aleo and Salvatore A. Lombardo
RTEffect of HCI Degradation on the Variability of MOSFETSChen Zhou, Keith Jenkins, Pierce Chuang and Christos Vezyrtzis
RTTemperature and voltage effects on HTRB and HTGB stresses for AlGaN/GaN HEMTsOmar Chihani, Loic Theolier, Alain Benssousan, Jean-Yves Deletage, André Durier and Eric Woirgard
RTInteraction of Permeats During the Measurement of Permeation Coefficients of Dense Polymer Films Under Realistic ConditionsAndreas PiekarczykFraunhofer Institute for Solar Energy Systems, Xuqiang Xu, Michael Köhl and Karl-Anders Weiß
RTPolysilicon Resistor Stability Under Voltage Stress for Safe-Operating Area CharacterizationChristian Kendrick, Michael Cook, Jeff Gambino, Tracy Myers, Jiri Slezak and Yuichi Watanabe
RTReliability characteriscs of MIM capacitor studied using ΔC-F characteristicsSoo Cheol Kang, Sang Kyung Lee, Sunwoo Heo, Seung Mo Kim, Sung Kwan Lim and Byoung Hun Lee
SEInvestigation of Alpha-Induced Single Event Transient (SET) in 10 nm FinFET Logic CircuitTaiki Uemura
SEStudy of TID Effects on One Row Hammering using Gamma in DDR4 SDRAMsDonghyuk Yun, Myungsang Park, Chulseung Lim and Sanghyeon Baeg
SESensitivity to Soft Errors of NMOS and PMOS Transistors Evaluated by Latches with Stacking Structures in a 65 nm FDSOI ProcessKodai Yamada, Haruki Maruoka, Jun Furuta and Kazutoshi Kobayashi
SEEffects of MCU and SEU Accumulation on TMR in SRAM-based FPGAsHayden Rowberry, Andrew Keller, James Swift and Michael Wirthlin
SEDesign soft-error-aware circuits with power and speed optimizationHui Jiang, Hangfang Zhang, Balaji Narasimham, Lloyd Massengill and Bharat Bhuva
SESingle-Event Effects on Optical transceiverKurt Lezon, Shi-Jie Wen, Yie-Fong Dan, Rick Wong and Bharat Bhuva
SRWeibull Cumulative Distribution Function (CDF) Analysis with Life Expectancy Endurance Test Result of Power Window SwitchDave Lim
SRDevelopment of a Flexible Wearable Biometric Band and Smartphone Application for Remote User-MonitoringPradeep Lall, Hao Zhang and Rahul Lall
TXLow Frequency Noise in MoS2 Negative Capacitance Field-effect TransistorSami Alghamdi, Mengwei Si, Lingming Yang and Peide D. Ye
TXHot Carrier Effects on the RF performance degradation of nanoscale LNA SOI nFETsDimitris P Ioannou, Yue Tan, Ron Logan, Kenneth Bandy, Ravi Achanta, Ping-Chuan Wang, Dave Brochu and Mark Jaffe
TXHot Carrier Induced TDDB in HV MOS: Lifetime Model and Extrapolation to Use ConditionsGuido Sasse
TXKEY PARAMETERS DRIVING TRANSISTOR DEGRADATION IN ADVANCED STRAINED SIGE CHANNELSvincent huard, cheikh ndiaye, melissa arabi, Narendra Parihar, Xavier Federspiel, Souhir Mhira, Souvik Mahapatra and Alain Bravaix
TXPrediction of NBTI Stress and Recovery Time Kinetics in Si Capped SiGe p-MOSFETsNarendra Parihar and Souvik Mahapatra
TXInvestigation on the Amplitude Coupling Effect of Random Telegraph Noise (RTN) in Nanoscale FinFETsShaofeng Guo, Zhenghan Lin, Runsheng Wang, Zexuan Zhang, Zhe Zhang, Yangyuan Wang and Ru Huang
TXPBTI Evaluation of In0.65Ga0.35As/In0.53Ga0.47As Nanowire FETs with Al2O3 and LaAlO3 Gate DielectricsYun Li, Kunliang Wang, Shaoyan Di, Peng Huang, Gang Du and Xiaoyan Liu
TXInterface Engineering of Ferroelectric Negative Capacitance FET for Hysteresis-Free Switch and Reliability ImprovementChia-Chi Fan, Chun-Hu Cheng, Chien Liu, Chun-Yuan Tu, Guan-Lin Liou and Chun-Yen Chang
WBThreshold Voltage Shift and Interface/Border Trapping Mechanism in Al2O3/AlGaN/GaN MOS-HEMTsJiejie Zhu, Bin Hou, Lixiang Chen, Qing Zhu, Ling Yang, Minhan Mi, Xiaowei Zhou, Peng Zhang, Xiaohua Ma and Yue Hao
WBInvestigation of the Pulsed-IV Degradation Mechanism of GaN-HEMT under High Temperature Storage TestsYasunori Tateno, Yasuyo Kurachi, Hiroshi Yamamoto and Takashi Nakabayashi
WBFailure mode analysis of GaN-HEMT under high temperature operationYasuyo Kurachi, Yasunori Tateno, Takumi Yonemura, Masato Furukawa, Hiroshi Yamamoto, Yukinori Nose and Satoshi Shimizu
WBA novel GaN HEMT degradation mechanism observed during HTST testferdinando iucolano, antonino parisi, santo reina and alessandro chini
WBInvestigation of Degradation Phenomena in GaN-on-Si Power MIS-HEMTs under Source Current and Drain Bias StressesChih Yi Yang, Tian Li Wu, Tin En Hsieh and Edward Yi Chang