IRPS

International Roadmap for Devices and Systems

Application Benchmarking, Systems and Architecture, Emerging Research Devices

1:10 – 2:00 PM, Tuesday, April 4, 2017

 

Panel Moderator: Dr. William R. Tonti, Sr. Director, IEEE Future Directions

Biography: Dr. Tonti holds a BSEE from Northeastern University, an MSEE and a Ph.D. from the University of Vermont, and an MBA from St. Michael’s College. He worked for over 30 years at IBM in the area of semiconductor technology research. Dr. Tonti holds in excess of 290 patents, and has been recognized as an IBM master inventor, and as one of the world’s top patent family holders. His 250th patent has been transcribed into the U.S. Congressional Record. Dr. Tonti is a Fellow of the IEEE a past IEEE Reliability Society President, a recipient of the IEEE Reliability Engineer of the Year award, and the IEEE 3’rd Millennium medal. Dr. Tonti currently is a senior IEEE staff director leading its future technology directions. Dr. Tonti is a past IRPS and IRW General Chair.

 

Panelist: Dr. Geoffrey Burr, Principal Research Staff Member, IBM

Topic/Focus Group: Application Benchmarking

Abstract: One of the driving forces behind the evolution of ITRS (International Technology Roadmap for Semiconductors) into IRDS (International Roadmap for Devices and Systems) is the need to track both devices and systems. In the computer industry, “benchmarking” refers to the use of test programs that serve as proxies for user applications to estimate the performance of a computer system — past, present or future — on a given application domain. Within IRDS, the Applications Benchmarking (AB) International Focus Team seeks to identify key application drivers, to match these to the market drivers identified by the Systems and Architectures IFT, and then to track and roadmap system performance through relevant benchmarks. I will discuss how this connects to underlying device performance including reliability.

Biography: Geoffrey W. Burr received his Ph.D. in Electrical Engineering from the California Institute of Technology in 1996. Since that time, Dr. Burr has worked at IBM Research–Almaden in San Jose, California, where he is currently a Principal Research Staff Member. He has worked in a number of diverse areas, including holographic data storage, photon echoes, computational electromagnetics, nanophotonics, computational lithography, phase-change memory, storage class memory, and novel access devices based on Mixed-Ionic-Electronic-Conduction (MIEC) materials. Dr. Burr’s current research interests  include non-volatile memory and cognitive computing. An IEEE Senior Member, Geoff is also a member of MRS, SPIE, OSA, Tau Beta Pi, Eta Kappa Nu, and the Institute of Physics (IOP).

 

Panelist: Dr. Erik DeBenedictus, Sandia National Labs

Topic/Focus Group: Systems and Architecture

Abstract: Future architectures in IRDS. The ITRS->IRDS had narrowed the scope of Moore’s 1965 paper to the microprocessor and DRAM memory. It is pretty clear that “Moore’s law has ended” for code written for single core microprocessors. However, new architectures are in development/production that continue historical rates of progress provided that software can be rewritten. I’ll describe the way new architectures can and will keep up the growth rate of Moore’s law.

Biography: Ph. D. from Caltech 1983. Worked on parallel computers at Bell labs, finite element software at Ansoft corporation, parallel computers at nCUBE. Currently working on “Beyond Moore’s law” research issues now at Sandia.

 

Panelist: Dr. Matthew Marinella, Principal Member of the Technical Staff, Sandia National Labs

Topic/Focus Group: Emerging Research Devices

Abstract: Low voltage logic switches and novel memory devices are the key building blocks for the next generation of computers. Using properties of these devices, such as low voltage digital and parallel analog operations will pave the way to several orders of magnitude improvement in key applications benchmarks like performance and features per watt. Research progress on the most promising emerging devices and how they will enable advanced computing have been tracked and assessed over many generations in the ITRS Emerging Research Devices Chapter, and this work continues as a core function of the IEEE International Roadmap for Devices and Systems Beyond CMOS Chapter.

Biography: Matthew Marinella is a Principal Member of the Technical Staff with Sandia National Labs. He leads several efforts focused on novel memory and neuromorphic computing, and is the Lead Scientist for Sandia’s Beyond Moore Computing Research Challenge. Dr. Marinella chairs the Emerging Memory Devices Section for the IRDS Roadmap Beyond CMOS Chapter and serves on the technical program committee for IEEE International Conference on Rebooting Computing. He received a PhD in electrical engineering from Arizona State University under Dieter Schroder in 2008.